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Freescale Semiconductor
Technical Data
Document Number: MPC8533EEC Rev. 3, 11/2009
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications
1 MPC8533E Overview
Contents MPC8533E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 17 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Enhanced Three-Speed Ethernet (eTSEC), MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ethernet Management Interface Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Programmable Interrupt Controller . . . . . . . . . . . . . 51 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 60 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 78 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 System Design Information . . . . . . . . . . . . . . . . . . 102 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 111 Document Revision History . . . . . . . . . . . . . . . . . . 114
This section provides a high-level overview of MPC8533E features. Figure 1 shows the major functional units within the device.
1.1
Key Features
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23.
The following list provides an overview of the device feature set: * High-performance 32-bit Book E-enhanced core built on Power ArchitectureTM technology: -- 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis, with separate locking for instructions and data. -- Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive instruction set for vector (64-bit) integer and fractional operations. These instructions use both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.
(c) Freescale Semiconductor, Inc., 2008, 2009. All rights reserved.
MPC8533E Overview
-- Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs. -- 36-bit real addressing -- Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for single-precision (32-bit) floating-point instructions. -- Memory management unit (MMU). Especially designed for embedded applications. Supports 4-Kbyte-4-Gbyte page sizes. -- Enhanced hardware and software debug support -- Performance monitor facility that is similar to, but separate from, the device performance monitor The e500 defines features that are not implemented on this device. It also generally defines some features that this device implements more specifically. An understanding of these differences can be critical to ensure proper operations. * 256-Kbyte L2 cache/SRAM -- Flexible configuration -- Full ECC support on 64-bit boundary in both cache and SRAM modes -- Cache mode supports instruction caching, data caching, or both. -- External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing). - 1, 2, or 4 ways can be configured for stashing only. -- Eight-way set-associative cache organization (32-byte cache lines) -- Supports locking entire cache or selected lines. Individual line locks are set and cleared through Book E instructions or by externally mastered transactions. -- Global locking and flash clearing done through writes to L2 configuration registers -- Instruction and data locks can be flash cleared separately. -- SRAM features include the following: - I/O devices access SRAM regions by marking transactions as snoopable (global). - Regions can reside at any aligned location in the memory map. - Byte-accessible ECC is protected using read-modify-write transaction accesses for smaller-than-cache-line accesses. * Address translation and mapping unit (ATMU) -- Eight local access windows define mapping within local 36-bit address space. -- Inbound and outbound ATMUs map to larger external address spaces. - Three inbound windows plus a configuration window on PCI and PCI Express - Four outbound windows plus default translation for PCI and PCI Express * DDR/DDR2 memory controller -- Programmable timing supporting DDR and DDR2 SDRAM -- 64-bit data interface
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MPC8533E Overview
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Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports Full ECC support Page mode support - Up to 16 simultaneous open pages for DDR - Up to 32 simultaneous open pages for DDR2 -- Contiguous or discontiguous memory mapping -- Sleep mode support for self-refresh SDRAM -- On-die termination support when using DDR2 -- Supports auto refreshing -- On-the-fly power management using CKE signal -- Registered DIMM support -- Fast memory access via JTAG port -- 2.5-V SSTL_2 compatible I/O (1.8-V SSTL_1.8 for DDR2) Programmable interrupt controller (PIC) -- Programming model is compliant with the OpenPIC architecture. -- Supports 16 programmable interrupt and processor task priority levels -- Supports 12 discrete external interrupts -- Supports 4 message interrupts with 32-bit messages -- Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller -- Four global high resolution timers/counters that can generate interrupts -- Supports a variety of other internal interrupt sources -- Supports fully nested interrupt delivery -- Interrupts can be routed to external pin for external processing. -- Interrupts can be routed to the e500 core's standard or critical interrupt inputs. -- Interrupt summary registers allow fast identification of interrupt source. Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP -- Four crypto-channels, each supporting multi-command descriptor chains - Dynamic assignment of crypto-execution units via an integrated controller - Buffer size of 256 bytes for each execution unit, with flow control for large data sizes -- PKEU--public key execution unit - RSA and Diffie-Hellman; programmable field size up to 2048 bits - Elliptic curve cryptography with F2m and F(p) modes and programmable field size up to 511 bits -- DEU--Data Encryption Standard execution unit - DES, 3DES
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3
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MPC8533E Overview
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- Two key (K1, K2, K1) or three key (K1, K2, K3) - ECB and CBC modes for both DES and 3DES -- AESU--Advanced Encryption Standard unit - Implements the Rijndael symmetric key cipher - ECB, CBC, CTR, and CCM modes - 128-, 192-, and 256-bit key lengths -- AFEU--ARC four execution unit - Implements a stream cipher compatible with the RC4 algorithm - 40- to 128-bit programmable key -- MDEU--message digest execution unit - SHA with 160- or 256-bit message digest - MD5 with 128-bit message digest - HMAC with either algorithm -- KEU--Kasumi execution unit - Implements F8 algorithm for encryption and F9 algorithm for integrity checking - Also supports A5/3 and GEA-3 algorithms -- RNG--random number generator -- XOR engine for parity checking in RAID storage applications Dual I2C controllers -- Two-wire interface -- Multiple master support -- Master or slave I2C mode support -- On-chip digital filtering rejects spikes on the bus Boot sequencer -- Optionally loads configuration data from serial ROM at reset via the I2C interface -- Can be used to initialize configuration registers and/or memory -- Supports extended I2C addressing mode -- Data integrity checked with preamble signature and CRC DUART -- Two 4-wire interfaces (SIN, SOUT, RTS, CTS) -- Programming model compatible with the original 16450 UART and the PC16550D Local bus controller (LBC) -- Multiplexed 32-bit address and data bus operating at up to 166 MHz -- Eight chip selects support eight external slaves -- Up to eight-beat burst transfers -- The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. -- Two protocol engines available on a per chip select basis:
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 4 Freescale Semiconductor
MPC8533E Overview
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- General-purpose chip select machine (GPCM) - Three user programmable machines (UPMs) -- Parity support -- Default boot ROM chip select with configurable bus width (8, 16, or 32 bits) Two enhanced three-speed Ethernet controllers (eTSECs) -- Three-speed support (10/100/1000 Mbps) -- Two IEEE Std 802.3(R), IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3ac, and IEEE 802.3ab-compliant controllers -- Support for various Ethernet physical interfaces: - 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, and RGMII. - 10/100 Mbps full- and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII. -- Flexible configuration for multiple PHY interface configurations. -- TCP/IP acceleration and QoS features available - IP v4 and IP v6 header recognition on receive - IP v4 header checksum verification and generation - TCP and UDP checksum verification and generation - Per-packet configurable acceleration - Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS stacks, and ESP/AH IP-security headers - Supported in all FIFO modes -- Quality of service support: - Transmission from up to eight physical queues - Reception to up to eight physical queues -- Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex): - IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or software-programmed PAUSE frame generation and recognition) -- Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and IEEE Std 802.1TM virtual local area network (VLAN) tags and priority -- VLAN insertion and deletion - Per-frame VLAN control word or default VLAN for each eTSEC - Extracted VLAN control word passed to software separately -- Retransmission following a collision -- CRC generation and verification of inbound/outbound frames -- Programmable Ethernet preamble insertion and extraction of up to 7 bytes -- MAC address recognition: - Exact match on primary and virtual 48-bit unicast addresses - VRRP and HSRP support for seamless router fail-over - Up to 16 exact-match MAC addresses supported
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
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MPC8533E Overview
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- Broadcast address (accept/reject) - Hash table match on up to 512 multicast addresses - Promiscuous mode -- Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet programming models -- RMON statistics support -- 10-Kbyte internal transmit and 2-Kbyte receive FIFOs -- MII management interface for control and status -- Ability to force allocation of header information and buffer descriptors into L2 cache OCeaN switch fabric -- Full crossbar packet switch -- Reorders packets from a source based on priorities -- Reorders packets to bypass blocked packets -- Implements starvation avoidance algorithms -- Supports packets with payloads of up to 256 bytes Integrated DMA controller -- Four-channel controller -- All channels accessible by both the local and remote masters -- Extended DMA functions (advanced chaining and striding capability) -- Support for scatter and gather transfers -- Misaligned transfer capability -- Interrupt on completed segment, link, list, and error -- Supports transfers to or from any local memory or I/O port -- Selectable hardware-enforced coherency (snoop/no snoop) -- Ability to start and flow control each DMA channel from external 3-pin interface -- Ability to launch DMA from single write transaction PCI controller -- PCI 2.2 compatible -- One 32-bit PCI port with support for speeds from 16 to 66 MHz -- Host and agent mode support -- 64-bit dual address cycle (DAC) support -- Supports PCI-to-memory and memory-to-PCI streaming -- Memory prefetching of PCI read accesses -- Supports posting of processor-to-PCI and PCI-to-memory writes -- PCI 3.3-V compatible -- Selectable hardware-enforced coherency
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 6 Freescale Semiconductor
MPC8533E Overview
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Three PCI Express interfaces -- Two x4 link width interfaces and one x1 link width interface -- PCI Express 1.0a compatible -- Auto-detection of number of connected lanes -- Selectable operation as root complex or endpoint -- Both 32- and 64-bit addressing -- 256-byte maximum payload size -- Virtual channel 0 only -- Traffic class 0 only -- Full 64-bit decode with 32-bit wide windows Power management -- Supports power saving modes: doze, nap, and sleep -- Employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle System performance monitor -- Supports eight 32-bit counters that count the occurrence of selected events -- Ability to count up to 512 counter-specific events -- Supports 64 reference events that can be counted on any of the 8 counters -- Supports duration and quantity threshold counting -- Burstiness feature that permits counting of burst events with a programmable time between bursts -- Triggering and chaining capability -- Ability to generate an interrupt on overflow System access port -- Uses JTAG interface and a TAP controller to access entire system memory map -- Supports 32-bit accesses to configuration registers -- Supports cache-line burst accesses to main memory -- Supports large block (4-Kbyte) uploads and downloads -- Supports continuous bit streaming of entire block for fast upload and download IEEE Std 1149.1TM-compliant, JTAG boundary scan 783 FC-PBGA package
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 7
Electrical Characteristics
MPC8533E
XOR Acceleration
e500 Core 32-Kbyte I-Cache 32-Kbyte D-Cache
256-Kbyte L2 Cache
Local Bus
Security Acceleration
OpenPIC
e500 Coherency Module
64-Bit DDR/DDR2 SDRAM Controller
Performance Monitor DUART 2x I2C
Gigabit Ethernet
32-Bit PCI PCI Express x1
PCI Express x4/x2/x1 PCI Express x4/x2/x1
DMA
Figure 1. MPC8533E Block Diagram
2
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8533E. This device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings1
Characteristic Symbol VDD AVDD SVDD XVDD Max Value -0.3 to 1.1 -0.3 to 1.1 -0.3 to 1.1 -0.3 to 1.1 Unit V V V V Notes -- -- -- --
Table 1 provides the absolute maximum ratings.
Core supply voltage PLL supply voltage Core power supply for SerDes transceivers Pad power supply for SerDes transceivers
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 8 Freescale Semiconductor
Electrical Characteristics
Table 1. Absolute Maximum Ratings1 (continued)
Characteristic DDR and DDR2 DRAM I/O voltage Three-speed Ethernet I/O, MII management voltage Symbol GVDD LVDD (eTSEC1) TVDD (eTSEC3) PCI, DUART, system control and power management, I2C, and JTAG I/O voltage Local bus I/O voltage OV DD BVDD Max Value -0.3 to 2.75 -0.3 to 1.98 -0.3 to 3.63 -0.3 to 2.75 -0.3 to 3.63 -0.3 to 2.75 -0.3 to 3.63 -0.3 to 3.63 -0.3 to 2.75 -0.3 to 1.98 -0.3 to (GV DD + 0.3) -0.3 to (GV DD + 0.3) -0.3 to (LVDD + 0.3) -0.3 to (TVDD + 0.3) -0.3 to (BVDD + 0.3) -0.3 to (OV DD + 0.3) -0.3 to (OV DD + 0.3) -55 to 150 Unit V V V V V Notes -- -- -- -- --
Input voltage
DDR/DDR2 DRAM signals DDR/DDR2 DRAM reference Three-speed Ethernet signals Local bus signals DUART, SYSCLK, system control and power management, I2C, and JTAG signals PCI
MVIN MVREF LVIN TVIN BVIN OVIN OVIN TSTG
V V V V V V C
2 2 2 -- 2 2 --
Storage temperature range
Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause. 2. (M,L,O)VIN, and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
2.1.2
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for this device. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Characteristic Core supply voltage PLL supply voltage Core power supply for SerDes transceivers Pad power supply for SerDes transceivers DDR and DDR2 DRAM I/O voltage Symbol VDD AVDD SVDD XVDD GVDD Recommended Value 1.0 50 mV 1.0 50 mV 1.0 50 mV 1.0 50 mV 2.5 V 125 mV 1.8 V 90 mV Unit V V V V V Notes -- 1 -- -- 2
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 9
Electrical Characteristics
Table 2. Recommended Operating Conditions (continued)
Characteristic Three-speed Ethernet I/O voltage Symbol LVDD (eTSEC1) TVDD (eTSEC3) PCI, DUART, PCI Express, system control and power management, I2C, and JTAG I/O voltage Local bus I/O voltage OV DD BVDD Recommended Value 3.3 V 165 mV 2.5 V 125 mV 3.3 V 165 mV 2.5 V 125 mV 3.3 V 165 mV 3.3 V 165 mV 2.5 V 125 mV 1.8 V 90 mV GND to GVDD GND to GVDD/2 GND to LVDD GND to TVDD GND to BVDD GND to OVDD 0 to 90 V V 3 5 Unit V Notes 4
Input voltage
DDR and DDR2 DRAM signals DDR and DDR2 DRAM reference Three-speed Ethernet signals Local bus signals PCI, Local bus, DUART, SYSCLK, system control and power management, I2C, and JTAG signals
MVIN MVREF LVIN TVIN BVIN OVIN Tj
V V V V V C
2 2 4 5 3 --
Junction temperature range
Notes: 1. This voltage is the input to the filter discussed in Section 21.2, "PLL Power Supply Filtering," and not necessarily the voltage at the AVDD pin, which may be reduced from V DD by the filter. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: T/LVIN must not exceed T/ LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. Caution: BVIN must not exceed BV DD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 10 Freescale Semiconductor
Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8533E.
B/G/L/OV DD + 20% B/G/L/OV DD + 5% VIH B/G/L/OVDD
GND GND - 0.3 V VIL GND - 0.7 V Not to Exceed 10% of t CLOCK1
Notes: 1. tCLOCK refers to the clock period associated with the respective interface: For I2C and JTAG, tCLOCK references SYSCLK. For DDR, tCLOCK references MCLK. For eTSEC, tCLOCK references EC_GTX_CLK125. For LBIU, tCLOCK references LCLK. For PCI, tCLOCK references PCI_CLK or SYSCLK. 2. Please note that with the PCI overshoot allowed (as specified above), the device does not fully comply with the maximum AC ratings and device protection guideline outlined in Section 4.2.2.3 of the PCI 2.2 Local Bus Specifications.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD/BVDD/TVDD
The core voltage must always be provided at nominal 1.0 V (see Table 2 for actual recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 SDRAM interface uses a single-ended differential receiver referenced the externally supplied MVREF signal (nominally set to GVDD/2) as is appropriate for the SSTL2 electrical signaling standard.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 11
Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3. Output Drive Capability
Driver Type Programmable Output Impedance () 25 35 45 (default) 45 (default) 125 Supply Voltage BVDD = 3.3 V BVDD = 2.5 V BVDD = 3.3 V BVDD = 2.5 V BVDD = 1.8 V OVDD = 3.3 V GVDD = 2.5 V GVDD = 1.8 V LVDD = 2.5/3.3 V OVDD = 3.3 V OVDD = 3.3 V 2 Notes 1
Table 3 provides information on the characteristics of the output driver strengths.
Local bus interface utilities signals
PCI signals
25 42 (default)
DDR signal DDR2 signal TSEC signals DUART, system control, JTAG I
2C
20 16 32 (half strength mode) 42 42 150
-- -- -- -- --
Notes: 1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR. 2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.
2.2
Power Sequencing
The device requires its power rails to be applied in specific sequence in order to ensure proper device operation. These requirements are as follows for power up: 1. VDD, AVDD_n, BVDD, LVDD, SVDD, OVDD, TVDD, XVDD 2. GVDD Note that all supplies must be at their stable values within 50 ms. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. In order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power up, then the sequencing for GVDD is not required. From a system standpoint, if any of the I/O power supplies ramp prior to the VDD core supply, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 12 Freescale Semiconductor
Power Characteristics
3
Power Characteristics
Table 4. MPC8533E Core Power Dissipation
Power Mode Core Frequency (MHz) 667 Platform Frequency (MHz) 333 VDD (V) 1.0 Junction Temperature (C) 65 90 Power (W) 2.6 3.75 5.85 800 400 1.0 65 90 2.9 4.0 6.0 1000 400 1.0 65 90 3.6 4.4 6.2 1067 533 1.0 65 90 3.9 5.0 6.5 Notes 1, 2 1, 3 1, 4 1, 2 1, 3 1, 4 1, 2 1, 3 1, 4 1, 2 1, 3 1, 4
The estimated typical core power dissipation for the core complex bus (CCB) versus the core frequency for this family of PowerQUICC III devices is shown in Table 4.
Typical Thermal Maximum Typical Thermal Maximum Typical Thermal Maximum Typical Thermal Maximum
Notes: 1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations. The values do not include power dissipation for I/O supplies. 2. Typical power is an average value measured at the nominal recommended core voltage (V DD) and 65C junction temperature (see Table 2) while running the Dhrystone 2.1 benchmark. 3. Thermal power is the average power measured at nominal core voltage (V DD) and maximum operating junction temperature (see Table 2) while running the Dhrystone 2.1 benchmark. 4. Maximum power is the maximum power measured at nominal core voltage (VDD) and maximum operating junction temperature (see Table 2) while running a smoke test which includes an entirely L1-cache-resident, contrived sequence of instructions which keep the execution unit maximally busy.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 13
Input Clocks
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4.1
Input Clocks
System Clock Timing
Table 5. SYSCLK AC Timing Specifications
Table 5 provides the system clock (SYSCLK) AC timing specifications for the MPC8533E.
At recommended operating conditions (see Table 2) with OVDD = 3.3 V 165 mV.
Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle SYSCLK jitter
Symbol fSYSCLK tSYSCLK tKH, tKL tKHK/tSYSCLK --
Min 33 7.5 0.6 40 --
Typical -- -- 1.0 -- --
Max 133 30.3 2.1 60 150
Unit MHz ns ns % ps
Notes 1 -- 2 -- 3, 4
Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 19.2, "CCB/SYSCLK PLL Ratio," and Section 19.3, "e500 Core PLL Ratio," for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V. 3. This represents the total input jitter--short- and long-term. 4. The SYSCLK driver's closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
4.1.1
SYSCLK and Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and government requirements. These clock sources intentionally add long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 5 considers short-term (cycle-to-cycle) jitter only and the clock generator's cycle-to-cycle output jitter should meet the MPC8533E input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns, and the MPC8533E is compatible with spread spectrum sources if the recommendations listed in Table 6 are observed.
Table 6. Spread Spectrum Clock Source Recommendations
At recommended operating conditions. See Table 2.
Parameter Frequency modulation Frequency spread
Min 20 0
Max 60 1.0
Unit kHz %
Notes -- 1
Note: 1. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the minimum and maximum specifications given in Table 5.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 14 Freescale Semiconductor
Input Clocks
It is imperative to note that the processor's minimum and maximum SYSCLK, core, and VCO frequencies must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is operated at its maximum rated e500 core frequency should avoid violating the stated limits by using down-spreading only.
4.2
Real-Time Clock Timing
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC signal should be greater than 2 x the period of the CCB clock. That is, minimum clock high time is 2 x tCCB, and minimum clock low time is 2 x tCCB. There is no minimum RTC frequency; RTC may be grounded if not needed.
4.3
eTSEC Gigabit Reference Clock Timing
Table 7 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the MPC8533E.
Table 7. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition EC_GTX_CLK125 frequency EC_GTX_CLK125 cycle time EC_GTX_CLK rise and fall time LVDD, TVDD = 2.5 V LVDD, TVDD = 3.3 V EC_GTX_CLK125 duty cycle GMII, TBI 1000Base-T for RGMII, RTBI Symbol fG125 tG125 tG125R/tG125F Min -- -- -- Typ 125 8 -- 0.75 1.0 tG125H/tG125 45 47 -- 55 53 % 2 Max -- -- Unit MHz ns ns Notes -- -- 1
Notes: 1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for L/TVDD = 2.5 V, and from 0.6 and 2.7 V for L/TVDD = 3.3 V. 2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC GTX_CLK. See Section 8.5.4, "RGMII and RTBI AC Timing Specifications," for duty cycle for 10Base-T and 100Base-T reference clock.
4.4
Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed. For FIFO GMII mode: FIFO TX/RX clock frequency platform clock frequency / 4.2 For example, if the platform frequency is 533 MHz, the FIFO Tx/Rx clock frequency should be no more than 127 MHz.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 15
RESET Initialization
For FIFO encoded mode: FIFO TX/RX clock frequency platform clock frequency / 3.2 For example, if the platform frequency is 533 MHz, the FIFO Tx/Rx clock frequency should be no more than 167 MHz.
4.5
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific section of this document.
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8533E. Table 8 provides the RESET initialization AC timing specifications for the DDR SDRAM component(s).
Table 8. RESET Initialization Timing Specifications1
Parameter/Condition Required assertion time of HREST Minimum assertion time for SRESET PLL input setup time with stable SYSCLK before HRESET negation Input setup time for POR configs (other than PLL config) with respect to negation of HRESET Input hold time for all POR configs (including PLL config) with respect to negation of HRESET Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of HRESET Note: 1. SYSCLK is the primary clock input for the MPC8533E. Min 100 3 100 4 2 -- Max -- -- -- -- -- 5 Unit s SYSCLKs s SYSCLKs SYSCLKs SYSCLKs Notes -- 1 -- 1 1 1
Table 9 provides the PLL lock times.
Table 9. PLL Lock Times
Parameter/Condition Core and platform PLL lock times Local bus PLL PCI bus lock time Min -- -- -- Max 100 50 50 Unit s s s Notes -- -- --
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DDR and DDR2 SDRAM
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8533E. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
6.1
DDR SDRAM DC Electrical Characteristics
Table 10 provides the recommended operating conditions for the DDR SDRAM component(s) of the MPC8533E when GVDD(typ) = 1.8 V.
Table 10. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.26 V) Output low current (VOUT = 0.33 V) Symbol GVDD MVREF VTT VIH VIL IOZ IOH IOL Min 1.71 0.49 x GVDD MVREF - 0.04 MVREF + 0.26 -0.3 -50 -13.4 13.4 Max 1.89 0.51 x GVDD MVREF + 0.04 GVDD + 0.3 MVREF - 0.24 50 -- -- Unit V V V V V A mA mA Notes 1 2 3 -- -- 4 -- --
Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MV REF is expected to be equal to 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MV REF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
Table 11 provides the DDR2 I/O capacitance when GVDD(typ) = 1.8 V.
Table 11. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1 1
Note: 1. This parameter is sampled. GVDD = 1.8 V 0.090 V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 17
DDR and DDR2 SDRAM
Table 12 provides the recommended operating conditions for the DDR SDRAM component(s) when GVDD(typ) = 2.5 V.
Table 12. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V
Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.8 V) Output low current (VOUT = 0.42 V) Symbol GVDD MVREF VTT VIH VIL IOZ IOH IOL Min 2.375 0.49 x GVDD MVREF - 0.04 MVREF + 0.31 -0.3 -50 -16.2 16.2 Max 2.625 0.51 x GVDD MVREF + 0.04 GVDD + 0.3 MVREF - 0.3 50 -- -- Unit V V V V V A mA mA Notes 1 2 3 -- -- 4 -- --
Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MV REF is expected to be equal to 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MV REF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
Table 13 provides the DDR I/O capacitance when GVDD(typ) = 2.5 V.
Table 13. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V
Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1 1
Note: 1. This parameter is sampled. GVDD = 2.5 V 0.125 V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 14 provides the current draw characteristics for MVREF.
Table 14. Current Draw Characteristics for MVREF
Parameter/Condition Current draw for MVREF Symbol IMVREF Min -- Max 500 Unit A Notes 1
Note: 1. The voltage regulator for MVREF must be able to supply up to 500 A current.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 18 Freescale Semiconductor
DDR and DDR2 SDRAM
6.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR SDRAM Input AC Timing Specifications
Table 15. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Table 15 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 1.8 V.
At recommended operating conditions.
Parameter AC input low voltage AC input high voltage
Symbol VIL VIH
Min -- MVREF + 0.25
Max MVREF - 0.25 --
Unit V V
Notes -- --
Table 16 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 2.5 V.
Table 16. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions.
Parameter AC input low voltage AC input high voltage
Symbol VIL VIH
Min -- MVREF + 0.31
Max MVREF - 0.31 --
Unit V V
Notes -- --
Table 17 provides the input AC timing specifications for the DDR SDRAM interface.
Table 17. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions.
Parameter Controller skew for MDQS--MDQ/MECC/MDM 533 MHz 400 MHz 333 MHz
Symbol tCISKEW
Min
Max
Unit ps
Notes 1, 2 3 -- --
-300 -365 -390
300 365 390
Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be determined by the following equation: tDISKEW = (T/4 - abs(tCISKEW)), where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. See Figure 3. 3. Maximum DDR1 frequency is 400 MHz.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 19
DDR and DDR2 SDRAM
Figure 3 shows the DDR SDRAM input timing diagram.
MCK[n] MCK[n] tMCK MDQS[n]
MDQ[x]
D0 tDISKEW
D1 tDISKEW
Figure 3. DDR SDRAM Input Timing Diagram (tDISKEW)
6.2.2
DDR SDRAM Output AC Timing Specifications
Table 18. DDR SDRAM Output AC Timing Specifications
Table 18 provides the output AC timing specifications for the DDR SDRAM interface.
At recommended operating conditions.
Parameter MCK[n] cycle time, MCK[n]/MCK[n] crossing ADDR/CMD output setup with respect to MCK 533 MHz 400 MHz 333 MHz ADDR/CMD output hold with respect to MCK 533 MHz 400 MHz 333 MHz MCS[n] output setup with respect to MCK 533 MHz 400 MHz 333 MHz MCS[n] output hold with respect to MCK 533 MHz 400 MHz 333 MHz MCK to MDQS Skew
Symbol1 tMCK tDDKHAS
Min 3.75
Max 6
Unit ns ns
Notes 2 3 7
1.48 1.95 2.40 tDDKHAX 1.48 1.95 2.40 tDDKHCS 1.48 1.95 2.40 tDDKHCX 1.48 1.95 2.40 tDDKHMH -0.6
-- -- -- ns -- -- -- ns -- -- -- ns -- -- -- 0.6 ns
3 7 -- -- 3 7 -- -- 3 7 -- -- 4
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DDR and DDR2 SDRAM
Table 18. DDR SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions.
Parameter MDQ/MECC/MDM output setup with respect to MDQS 533 MHz 400 MHz 333 MHz MDQ/MECC/MDM output hold with respect to MDQS 533 MHz 400 MHz 333 MHz MDQS preamble MDQS postamble
Symbol1 tDDKHDS, tDDKLDS
Min
Max
Unit ps
Notes 5 7 -- --
538 700 900 tDDKHDX, tDDKLDX 538 700 900 tDDKHMP tDDKHME 0.75 x tMCK 0.4 x tMCK
-- -- -- ps -- -- -- -- 0.6 x tMCK ns ns
5 7 -- -- 6 6
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the MPC8533E PowerQUICC III Integrated Communications Processor Reference Manual, for a description and understanding of the timing modifications enabled by use of these bits. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the symbol conventions described in note 1. 7. Maximum DDR1 frequency is 400 MHz.
NOTE For the ADDR/CMD setup and hold specifications in Table 18, it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 21
DDR and DDR2 SDRAM
Figure 4 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
MCK[n] MCK[n] tMCK
tDDKHMH(max) = 0.6 ns
MDQS
tDDKHMH(min) = -0.6 ns
MDQS
Figure 4. Timing Diagram for tDDKHMH
Figure 5 shows the DDR SDRAM output timing diagram.
MCK MCK tMCK tDDKHAS, tDDKHCS tDDKHAX, tDDKHCX ADDR/CMD Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP
Figure 5. DDR and DDR2 SDRAM Output Timing Diagram
Figure 6 provides the AC test load for the DDR bus.
Output Z0 = 50 RL = 50 GVDD/2
Figure 6. DDR AC Test Load
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DUART
7
DUART
This section describes the DC and AC electrical specifications for the DUART interface of the MPC8533E.
7.1
DUART DC Electrical Characteristics
Table 19. DUART DC Electrical Characteristics
Parameter Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- 2.4 -- Max OVDD + 0.3 0.8 5 -- 0.4 Unit V V A V V Notes -- -- 1 -- --
Table 19 provides the DC electrical characteristics for the DUART interface.
High-level input voltage Low-level input voltage Input current (V IN = 0 V or VIN = VDD) High-level output voltage (OVDD = min, IOH = -2 mA) Low-level output voltage (OVDD = min, IOL = 2 mA)
Note: 1. Note that the symbol VIN, in this case, represents the OV IN symbol referenced in Table 1 and Table 2.
7.2
DUART AC Electrical Specifications
Table 20. DUART AC Timing Specifications
Parameter Value CCB clock/1,048,576 CCB clock/16 16 Unit baud baud -- Notes 1 2 3
Table 20 provides the AC timing parameters for the DUART interface.
Minimum baud rate Maximum baud rate Oversample rate
Notes: 1. CCB clock refers to the platform clock. 2. Actual attainable baud rate will be limited by the latency of interrupt processing. 3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each sixteenth sample.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 23
Enhanced Three-Speed Ethernet (eTSEC), MII Management
8
Enhanced Three-Speed Ethernet (eTSEC), MII Management
This section provides the AC and DC electrical characteristics for enhanced three-speed and MII management.
8.1
Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps)--GMII/MII/TBI/RGMII/RTBI/RMII/FIFO Electrical Characteristics
The electrical characteristics specified here apply to all gigabit media independent interface (GMII), 8-bit FIFO interface (FIFO), media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals except management data input/output (MDIO) and management data clock (MDC). The 8-bit FIFO interface can operate at 3.3 or 2.5 V. The RGMII and RTBI interfaces are defined for 2.5 V, while the MII, GMII, TBI, and RMII interfaces can be operated at 3.3 or 2.5 V. Whether the GMII, MII, or TBI interface is operated at 3.3 or 2.5 V, the timing is compliant with IEEE 802.3. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII Specification Version 1.2 (3/20/1998). The electrical characteristics for MDIO and MDC are specified in Section 9, "Ethernet Management Interface Electrical Characteristics."
8.2
eTSEC DC Electrical Characteristics
All GMII, MII, TBI, RGMII, RTBI, RMII, and FIFO drivers and receivers comply with the DC parametric attributes specified in Table 21 and Table 22. The potential applied to the input of a GMII, MII, TBI, RTBI, RMII, and FIFO receiver may exceed the potential of the receiver's power supply (that is, a GMII driver powered from a 3.6-V supply driving VOH into a GMII receiver powered from a 2.5-V supply). Tolerance for dissimilar GMII driver and receiver supply potentials is implicit in these specifications. The RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 21. GMII, MII, TBI, RMII and FIFO DC Electrical Characteristics
Parameter Supply voltage 3.3 V Output high voltage (LVDD/TVDD = Min, IOH = -4.0 mA) Output low voltage (LV DD/TVDD = Min, IOL = 4.0 mA) Input high voltage Input low voltage Input high current (VIN = LVDD, VIN = TVDD) Symbol LVDD TVDD VOH VOL VIH VIL IIH Min 3.135 2.4 -- 1.95 -- -- Max 3.465 -- 0.5 -- 0.90 40 Unit V V V V V A Notes 1, 2 -- -- -- -- 1, 2, 3
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 24 Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 21. GMII, MII, TBI, RMII and FIFO DC Electrical Characteristics (continued)
Parameter Input low current (V IN = GND) Symbol IIL Min -600 Max -- Unit A Notes 3
Notes: 1. LVDD supports eTSEC1. 2. TVDD supports eTSEC3. 3. The symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 1 and Table 2.
Table 22. GMII, MII, RMII, RGMII, RTBI, TBI, and FIFO DC Electrical Characteristics
Parameters Supply voltage 2.5 V Output high voltage (LVDD/TVDD = Min, IOH = -1.0 mA) Output low voltage (LV DD/TVDD = Min, IOL = 1.0 mA) Input high voltage Input low voltage Input current (V IN = 0, VIN = LVDD, VIN = TVDD) Symbol LVDD/TVDD VOH VOL VIH VIL IIN Min 2.375 2.0 -- 1.70 -- -- Max 2.625 -- 0.4 -- 0.7 15 Unit V V V V V A Notes 1, 2 -- -- -- -- 1, 2, 3
Notes: 1. LVDD supports eTSEC1. 2. TVDD supports eTSEC3. 3. The symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 1 and Table 2.
8.3
FIFO, GMII,MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this section.
8.3.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC FIFO modes is the double data rate RGMII and RTBI specifications, since they have similar performance and are described in a source-synchronous fashion like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and source clock in GMII fashion. When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn TSECn_TX_CLK, while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source-synchronous timing reference. Typically, the clock edge that launched the data can be used, since the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 25
Enhanced Three-Speed Ethernet (eTSEC), MII Management
A summary of the FIFO AC specifications appears in Table 23 and Table 24.
Table 23. FIFO Mode Transmit AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V 5% or 2.5 V 5%
Parameter/Condition TX_CLK, GTX_CLK clock period TX_CLK, GTX_CLK duty cycle TX_CLK, GTX_CLK peak-to-peak jitter Rise time TX_CLK (20%-80%) Fall time TX_CLK (80%-20%) GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
Symbol tFIT tFITH tFITJ tFITR tFITF tFITDX
Min -- 45 -- -- -- 0.5
Typ 8.0 50 -- -- -- --
Max -- 55 250 0.75 0.75 3.0
Unit ns % ps ns ns ns
Notes -- -- -- -- -- 1
Note: 1. Data valid tFITDV to GTX_CLK Min setup time is a function of clock period and max hold time. (Min setup = Cycle time - Max hold).
Table 24. FIFO Mode Receive AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V 5% or 2.5 V 5%
Parameter/Condition RX_CLK clock period RX_CLK duty cycle RX_CLK peak-to-peak jitter Rise time RX_CLK (20%-80%) Fall time RX_CLK (80%-20%) RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RX_CLK to RXD[7:0], RX_DV, RX_ER hold time
Symbol tFIR tFIRH/tFIRH tFIRJ tFIRR tFIRF tFIRDV tFIRDX
Min -- 45 -- -- -- 1.5 0.5
Typ 8.0 50 -- -- -- -- --
Max -- 55 250 0.75 0.75 -- --
Unit ns % ps ns ns ns ns
Notes -- -- -- -- -- -- --
Timing diagrams for FIFO appear in Figure 7 and Figure 8.
tFIT tFITF tFITR
GTX_CLK
tFITH tFITDV tFITDX
TXD[7:0] TX_EN TX_ER
Figure 7. FIFO Transmit AC Timing Diagram
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 26 Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
tFIR
tFIRR
RX_CLK
tFIRH tFIRF
RXD[7:0] RX_DV RX_ER
tFIRDV
Valid Data tFIRDX
Figure 8. FIFO Receive AC Timing Diagram
8.3.2
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
8.3.2.1
GMII Transmit AC Timing Specifications
Table 25. GMII Transmit AC Timing Specifications
Table 25 provides the GMII transmit AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5% or 2.5 V 5%
Parameter/Condition GTX_CLK clock period GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK data clock rise time (20%-80%) GTX_CLK data clock fall time (80%-20%)
Symbol1 tGTX tGTKHDX tGTXR tGTXF
Min -- 0.2 -- --
Typ 8.0 -- -- --
Max -- 5.0 1.0 1.0
Unit ns ns ns ns
Notes -- 2 -- --
Notes: 1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Data valid tGTKHDV to GTX_CLK Min setup time is a function of clock period and max hold time (Min setup = cycle time - Max delay).
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 27
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 9 shows the GMII transmit AC timing diagram.
tGTX GTX_CLK tGTXH TXD[7:0] TX_EN TX_ER tGTKHDX tGTKHDV tGTXF tGTXR
Figure 9. GMII Transmit AC Timing Diagram
8.3.2.2
GMII Receive AC Timing Specifications
Table 26. GMII Receive AC Timing Specifications
Table 26 provides the GMII receive AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5% or 2.5 V 5%
Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RX_CLK to RXD[7:0], RX_DV, RX_ER hold time RX_CLK clock rise (20%-80%) RX_CLK clock fall time (80%-20%)
Symbol1 tGRX tGRXH/tGRX tGRDVKH tGRDXKH tGRXR tGRXF
Min -- 35 2.0 0.5 -- --
Typ 8.0 -- -- -- -- --
Max -- 65 -- -- 1.0 1.0
Unit ns % ns ns ns ns
Notes -- -- -- -- -- --
Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 10 provides the AC test load for eTSEC.
Output Z0 = 50 RL = 50 LVDD/2
Figure 10. eTSEC AC Test Load
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 28 Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 11 shows the GMII receive AC timing diagram.
tGRX RX_CLK tGRXH RXD[7:0] RX_DV RX_ER tGRDXKH tGRDVKH tGRXF tGRXR
Figure 11. GMII Receive AC Timing Diagram
8.4
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.4.1
MII Transmit AC Timing Specifications
Table 27. MII Transmit AC Timing Specifications
Table 27 provides the MII transmit AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5% or 2.5 V 5%
Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise (20%-80%) TX_CLK data clock fall (80%-20%)
Symbol1 tMTX tMTX tMTXH/tMTX tMTKHDX tMTXR tMTXF
Min -- -- 35 1 1.0 1.0
Typ 400 40 -- 5 -- --
Max -- -- 65 15 4.0 4.0
Unit ns ns % ns ns ns
Notes -- -- -- -- -- --
Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 29
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 12 shows the MII transmit AC timing diagram.
tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR
Figure 12. MII Transmit AC Timing Diagram
8.4.2
MII Receive AC Timing Specifications
Table 28. MII Receive AC Timing Specifications
Table 28 provides the MII receive AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5%.or 2.5 V 5%.
Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise (20%-80%) RX_CLK clock fall time (80%-20%)
Symbol1 tMRX tMRX tMRXH/tMRX tMRDVKH tMRDXKH tMRXR tMRXF
Min -- -- 35 10.0 10.0 1.0 1.0
Typ 400 40 -- -- -- -- --
Max -- -- 65 -- -- 4.0 4.0
Unit ns ns % ns ns ns ns
Notes -- -- -- -- -- -- --
Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 13 provides the AC test load for eTSEC.
Output Z0 = 50 RL = 50 LVDD/2
Figure 13. eTSEC AC Test Load
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 30 Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 14 shows the MII receive AC timing diagram.
tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKL tMRXF Valid Data tMRXR
Figure 14. MII Receive AC Timing Diagram
8.5
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.5.1
TBI Transmit AC Timing Specifications
Table 29. TBI Transmit AC Timing Specifications
Table 29 provides the TBI transmit AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5% or 2.5 V 5%..
Parameter/Condition GTX_CLK clock period GTX_CLK to TCG[9:0] delay time GTX_CLK rise (20%-80%) GTX_CLK fall time (80%-20%)
Symbol1 tGTX tTTKHDX tTTXR tTTXF
Min -- 0.2 -- --
Typ 8.0 -- -- --
Max -- 5.0 1.0 1.0
Unit ns ns ns ns
Notes -- 2 -- --
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Data valid tTTKHDV to GTX_CLK Min setup time is a function of clock period and max hold time (Min setup = cycle time - Max delay).
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Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 15 shows the TBI transmit AC timing diagram.
tTTX GTX_CLK tTTXH tTTXF tTTXR
TCG[9:0] tTTKHDV tTTKHDX
Figure 15. TBI Transmit AC Timing Diagram
8.5.2
TBI Receive AC Timing Specifications
Table 30. TBI Receive AC Timing Specifications
Table 30 provides the TBI receive AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5% or 2.5 V 5%.
Parameter/Condition PMA_RX_CLK[0:1] clock period PMA_RX_CLK[0:1] skew PMA_RX_CLK[0:1] duty cycle RCG[9:0] setup time to rising PMA_RX_CLK PMA_RX_CLK to RCG[9:0] hold time PMA_RX_CLK[0:1] clock rise time (20%-80%) PMA_RX_CLK[0:1] clock fall time (80%-20%)
Symbol1 tTRX tSKTRX tTRXH/tTRX tTRDVKH tTRDXKH tTRXR tTRXF
Min -- 7.5 40 2.5 1.5 0.7 0.7
Typ 16.0 -- -- -- -- -- --
Max -- 8.5 60 -- -- 2.4 2.4
Unit ns ns % ns ns ns ns
Notes -- -- -- -- -- -- --
Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX).
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Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 16 shows the TBI receive AC timing diagram.
tTRX PMA_RX_CLK1 tTRXH RCG[9:0] tTRDVKH tSKTRX PMA_RX_CLK0 tTRXH tTRDVKH tTRDXKH tTRDXKH tTRXF Valid Data Valid Data tTRXR
Figure 16. TBI Receive AC Timing Diagram
8.5.3
TBI Single-Clock Mode AC Specifications
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1, a 125-MHz TBI receive clock is supplied on the TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode, whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied on the TSEC_GTX_CLK125 pin in all TBI modes. A summary of the single-clock TBI mode AC specifications for receive appears in Table 31.
Table 31. TBI Single-Clock Mode Receive AC Timing Specification
Parameter/Condition RX_CLK clock period RX_CLK duty cycle RX_CLK peak-to-peak jitter Rise time RX_CLK (20%-80%) Fall time RX_CLK (80%-20%) RCG[9:0] setup time to RX_CLK rising edge RCG[9:0] hold time to RX_CLK rising edge Symbol tTRR tTRRH tTRRJ tTRRR tTRRF tTRRDV tTRRDX Min 7.5 40 -- -- -- 2.0 1.0 Typ 8.0 50 -- -- -- -- -- Max 8.5 60 250 1.0 1.0 -- -- Unit ns % ps ns ns ns ns Notes -- -- -- -- -- -- --
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 33
Enhanced Three-Speed Ethernet (eTSEC), MII Management
A timing diagram for TBI receive appears in Figure 17.
.
tTRR RX_CLK tTRRH tTRRF
tTRRR
RCG[9:0] tTRRDV
Valid Data tTRRDX
Figure 17. TBI Single-Clock Mode Receive AC Timing Diagram
8.5.4
RGMII and RTBI AC Timing Specifications
Table 32. RGMII and RTBI AC Timing Specifications
Table 32 presents the RGMII and RTBI AC timing specifications.
At recommended operating conditions with L/TVDD of 2.5 V 5%.
Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock period duration Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%-80%) Fall time (20%-80%)
Symbol1 tSKRGT_TX tSKRGT_RX tRGT tRGTH/tRGT tRGTR tRGTF
Min -500 1.0 7.2 40 -- --
Typ 0 -- 8.0 50 -- --
Max 500 2.8 8.8 60 0.75 0.75
Unit ps ns ns % ns ns
Notes 5 2 3 3, 4
Notes: 1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between. 5. Guaranteed by design.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 34 Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 18 shows the RGMII and RTBI AC timing and multiplexing diagrams.
tRGT tRGTH GTX_CLK (At Transmitter) tSKRGT_TX TXD[8:5][3:0] TXD[7:4][3:0] TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXEN TXD[9] TXERR tSKRGT_RX TX_CLK (At PHY)
TX_CTL
tRGTH GTX_CLK (At Receiver) RXD[8:5][3:0] RXD[7:4][3:0] RXD[8:5] RXD[3:0] RXD[7:4] tSKRGT_TX RX_CTL RXD[4] RXDV RXD[9] RXERR
tRGT
tSKRGT_RX RX_CLK (At PHY)
Figure 18. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.5.5
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.5.5.1
RMII Transmit AC Timing Specifications
Table 33. RMII Transmit AC Timing Specifications
The RMII transmit AC timing specifications are in Table 33.
At recommended operating conditions with L/TVDD of 3.3 V 5% or 2.5 V 5%.
Parameter/Condition REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%-80%) Fall time REF_CLK (80%-20%)
Symbol1 tRMT tRMTH tRMTJ tRMTR tRMTF
Min 15.0 35 -- 1.0 1.0
Typ 20.0 50 -- -- --
Max 25.0 65 250 2.0 2.0
Unit ns % ps ns ns
Notes -- -- -- -- --
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 35
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 33. RMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V 5% or 2.5 V 5%.
Parameter/Condition REF_CLK to RMII data TXD[1:0], TX_EN delay
Symbol1 tRMTDX
Min 1.0
Typ --
Max 10.0
Unit ns
Notes --
Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 19 shows the RMII transmit AC timing diagram.
tRMT REF_CLK tRMTH TXD[1:0] TX_EN TX_ER tRMTDX tRMTF tRMTR
Figure 19. RMII Transmit AC Timing Diagram
8.5.5.2
RMII Receive AC Timing Specifications
Table 34. RMII Receive AC Timing Specifications
Table 34 shows the RMII receive AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5%.or 2.5 V 5%.
Parameter/Condition REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%-80%) Fall time REF_CLK (80%-20%) RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge
Symbol1 tRMR tRMRH tRMRJ tRMRR tRMRF tRMRDV
Min 15.0 35 -- 1.0 1.0 4.0
Typ 20.0 50 -- -- -- --
Max 25.0 65 250 2.0 2.0 --
Unit ns % ps ns ns ns
Notes -- -- -- -- -- --
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 36 Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 34. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V 5%.or 2.5 V 5%.
Parameter/Condition RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge
Symbol1 tRMRDX
Min 2.0
Typ --
Max --
Unit ns
Notes --
Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 20 provides the AC test load for eTSEC.
Output Z0 = 50 RL = 50 LVDD/2
Figure 20. eTSEC AC Test Load
Figure 21 shows the RMII receive AC timing diagram.
tRMR REF_CLK tRMRH RXD[1:0] CRS_DV RX_ER tRMRDV tRMRDX tRMRF Valid Data tRMRR
Figure 21. RMII Receive AC Timing Diagram
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 37
Ethernet Management Interface Electrical Characteristics
9
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for GMII, RGMII, RMII, TBI, and RTBI are specified in "Section 8, "Enhanced Three-Speed Ethernet (eTSEC), MII Management."
9.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 35.
Table 35. MII Management DC Electrical Characteristics
Parameter Supply voltage (3.3 V) Output high voltage (OVDD = Min, IOH = -1.0 mA) Output low voltage (OVDD = Min, IOL = 1.0 mA) Input high voltage Input low voltage Input high current (OVDD = Max, VIN = 2.1 V) Input low current (OVDD = Max, VIN = 0.5 V) Symbol OVDD VOH VOL VIH VIL IIH IIL Min 3.135 2.10 GND 1.95 -- -- -600 Max 3.465 3.60 0.50 -- 0.90 40 -- Unit V V V V V A A Notes -- -- -- -- -- 1 --
Note: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
9.2
MII Management AC Electrical Specifications
Table 36. MII Management AC Timing Specifications
Table 36 provides the MII management AC timing specifications.
At recommended operating conditions with OVDD is 3.3 V 5%.
Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time
Symbol1 fMDC tMDC tMDCH tMDKHDX tMDDVKH tMDDXKH tMDCR
Min -- -- 32 (16 x tplb_clk) - 3 5 0 --
Typ 2.5 400 -- -- -- -- --
Max -- -- -- (16 x tplb_clk) + 3 -- -- 10
Unit MHz ns ns ns ns ns ns
Notes 2 -- -- 3, 4 -- -- --
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 38 Freescale Semiconductor
Ethernet Management Interface Electrical Characteristics
Table 36. MII Management AC Timing Specifications (continued)
At recommended operating conditions with OVDD is 3.3 V 5%.
Parameter/Condition MDC fall time
Symbol1 tMDHF
Min --
Typ --
Max 10
Unit ns
Notes --
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of the MgmtClk Clock EC_MDC). 3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods 3 ns. For example, with a platform clock of 333 MHz, the min/max delay is 48 ns 3 ns. Similarly, if the platform clock is 400 MHz, the min/max delay is 40 ns 3 ns). 4. tplb_clk is the platform (CCB) clock.
Figure 22 shows the MII management AC timing diagram.
tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX tMDCF tMDCR
Figure 22. MII Management Interface Timing Diagram
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 39
Local Bus
10 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the MPC8533E.
10.1
Local Bus DC Electrical Characteristics
Table 37 provides the DC electrical characteristics for the local bus interface operating at BVDD = 3.3 V DC.
Table 37. Local Bus DC Electrical Characteristics (3.3 V DC)
Parameter High-level input voltage Low-level input voltage Input current (BV IN = 0 V or BVIN = BOVDD) High-level output voltage (BVDD = min, IOH = -2 mA) Low-level output voltage (BV DD = min, IOL = 2 mA) Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- 2.4 -- Max BVDD + 0.3 0.8 5 -- 0.4 Unit V V A V V Notes -- -- 1 -- --
Note: 1. The symbol BVIN, in this case, represents the BVIN symbol referenced in Table 1 and Table 2.
Table 38 provides the DC electrical characteristics for the local bus interface operating at BVDD = 2.5 V DC.
Table 38. Local Bus DC Electrical Characteristics (2.5 V DC)
Parameter High-level input voltage Low-level input voltage Input current (BV IN = 0 V or BVIN = BVDD) High-level output voltage (BVDD = min, IOH = -1 mA) Low-level output voltage (BV DD = min, IOL = 1 mA) Symbol VIH VIL IIN VOH VOL Min 1.70 -0.3 -- 2.0 -- Max BVDD + 0.3 0.7 15 -- 0.4 Unit V V A V V Notes -- -- 1 -- --
Note: 1. The symbol BVIN, in this case, represents the BVIN symbol referenced in Table 1 and Table 2.
Table 39 provides the DC electrical characteristics for the local bus interface operating at BVDD = 1.8 V DC.
Table 39. Local Bus DC Electrical Characteristics (1.8 V DC)
Parameter High-level input voltage Low-level input voltage Input current (BV IN = 0 V or BVIN = BVDD) Symbol VIH VIL IIN Min 1.3 -0.3 -- Max BVDD + 0.3 0.6 15 Unit V V A Notes -- -- 1
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 40 Freescale Semiconductor
Local Bus
Table 39. Local Bus DC Electrical Characteristics (1.8 V DC) (continued)
Parameter High-level output voltage (BVDD = min, IOH = -2 mA) Low-level output voltage (BVDD = min, IOL = 2 mA) Symbol VOH VOL Min 1.35 Max -- Unit V Notes --
--
0.45
V
--
10.2
Local Bus AC Electrical Specifications
Table 40 describes the general timing parameters of the local bus interface at BVDD = 3.3 V. For information about the frequency range of local bus see Section 19.1, "Clock Ranges."
Table 40. Local Bus General Timing Parameters (BVDD = 3.3 V)--PLL Enabled
Parameter Local bus cycle time Local bus duty cycle LCLK[n] skew to LCLK[m] or LSYNC_OUT Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH setup and hold time) Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Symbol1 tLBK tLBKH/tLBK tLBKSKEW tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT tLBKHOV1 tLBKHOV2 tLBKHOV3 tLBKHOV4 tLBKHOX1 tLBKHOX2 tLBKHOZ1 Min 7.5 43 -- 2.5 1.85 1.0 1.0 1.5 -- -- -- -- 0.7 0.7 -- Max 12 57 150 -- -- -- -- -- 2.9 2.8 2.7 2.7 -- -- 2.5 Unit ns % ps ns ns ns ns ns ns ns ns ns ns ns ns Notes 2 -- 7, 8 3, 4 3, 4 3, 4 3, 4 6 -- -- 3 3 3 3 5
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 41
Local Bus
Table 40. Local Bus General Timing Parameters (BVDD = 3.3 V)--PLL Enabled (continued)
Parameter Local bus clock to output high impedance for LAD/LDP Symbol1 tLBKHOZ2 Min -- Max 2.5 Unit ns Notes 5
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t LBK clock reference (K) goes high (H), in this case for clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode. 3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL bypass mode to 0.4 x BVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is programmed with the LBCR[AHD] parameter. 7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BV DD/2.
Table 41 describes the general timing parameters of the local bus interface at BVDD = 2.5 V.
Table 41. Local Bus General Timing Parameters (BVDD = 2.5 V)--PLL Enabled
Parameter Local bus cycle time Local bus duty cycle LCLK[n] skew to LCLK[m] or LSYNC_OUT Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH setup and hold time) Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Symbol1 tLBK tLBKH/tLBK tLBKSKEW tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT tLBKHOV1 tLBKHOV2 tLBKHOV3 tLBKHOV4 tLBKHOX1 tLBKHOX2 tLBKHOZ1 Min 7.5 43 -- 2.4 1.8 1.1 1.1 1.5 -- -- -- -- 0.8 0.8 -- Max 12 57 150 -- -- -- -- -- 2.8 2.8 2.8 2.8 -- -- 2.6 Unit ns % ps ns ns ns ns ns ns ns ns ns ns ns ns Notes 2 -- 7 3, 4 3, 4 3, 4 3, 4 6 -- 3 3 3 3 3 5
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 42 Freescale Semiconductor
Local Bus
Table 41. Local Bus General Timing Parameters (BVDD = 2.5 V)--PLL Enabled (continued)
Parameter Local bus clock to output high impedance for LAD/LDP Symbol1 tLBKHOZ2 Min -- Max 2.6 Unit ns Notes 5
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode. 3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL bypass mode to 0.4 x BVDD of the signal in question for 2.5-V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is programmed with the LBCR[AHD] parameter. 7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BV DD/2.
Table 42 describes the general timing parameters of the local bus interface at BVDD = 1.8 V DC.
Table 42. Local Bus General Timing Parameters (BVDD = 1.8 V DC)
Parameter Local bus cycle time Local bus duty cycle LCLK[n] skew to LCLK[m] or LSYNC_OUT Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH setup and hold time) Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Symbol1 tLBK tLBKH/tLBK tLBKSKEW tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT tLBKHOV1 tLBKHOV2 tLBKHOV3 tLBKHOV4 tLBKHOX1 tLBKHOX2 tLBKHOZ1 Min 7.5 43 -- 2.6 1.9 1.1 1.1 1.2 -- -- -- -- 0.9 0.9 -- Max 12 57 150 -- -- -- -- -- 3.2 3.2 3.2 3.2 -- -- 2.6 Unit ns % ps ns ns ns ns ns ns ns ns ns ns ns ns Notes 2 -- 7 3, 4 3, 4 3, 4 3, 4 6 -- 3 3 3 3 3 5
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 43
Local Bus
Table 42. Local Bus General Timing Parameters (BVDD = 1.8 V DC) (continued)
Parameter Local bus clock to output high impedance for LAD/LDP Symbol1 tLBKHOZ2 Min -- Max 2.6 Unit ns Notes 5
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t LBK clock reference (K) goes high (H), in this case for clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode. 3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL bypass mode to 0.4 x BVDD of the signal in question for 1.8-V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is programmed with the LBCR[AHD] parameter. 7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BV DD/2.
Figure 23 provides the AC test load for the local bus.
Output Z0 = 50 RL = 50 BVDD/2
Figure 23. Local Bus AC Test Load
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 44 Freescale Semiconductor
Local Bus
Figure 24 through Figure 29 show the local bus signals.
LSYNC_IN tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIVKH2 Input Signal: LGTA tLBIXKH2 tLBIXKH1
LUPWAIT Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV3 Output (Address) Signal: LAD[0:31] tLBOTOT tLBKHOV4 LALE tLBKHOZ2 tLBKHOX2 tLBKHOV1 tLBKHOZ1 tLBKHOX1
tLBKHOV2
tLBKHOZ2 tLBKHOX2
Figure 24. Local Bus Signals (PLL Enabled)
Table 43 describes the general timing parameters of the local bus interface at VDD = 3.3 V DC with PLL disabled.
Table 43. Local Bus General Timing Parameters--PLL Bypassed
Parameter Local bus cycle time Local bus duty cycle Internal launch/capture clock to LCLK delay Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) Symbol1 tLBK tLBKH/tLBK tLBKHKT tLBIVKH1 tLBIVKL2 tLBIXKH1 tLBIXKL2 tLBOTOT tLBKLOV1 Min 12 43 1.2 7.4 6.75 -0.2 -0.2 1.5 -- Max -- 57 4.9 -- -- -- -- -- 1.6 Unit ns % ns ns ns ns ns ns ns Notes 2 -- -- 4, 5 4, 5 4, 5 4, 5 6 --
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 45
Local Bus
Table 43. Local Bus General Timing Parameters--PLL Bypassed (continued)
Parameter Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD, and LALE Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high impedance for LAD/LDP Symbol1 tLBKLOV2 tLBKLOV3 tLBKLOX1 tLBKLOX2 tLBKLOZ1 tLBKLOZ2 Min -- -- -4.1 -4.1 -- -- Max 1.6 1.6 -- -- 1.4 1.4 Unit ns ns ns ns ns ns Notes 4 4 4 4 7 7
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus clock because the actual launch and capture of signals is done with the internal launch/capture clock, which proceeds LCLK by tLBKHKT. 3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BV DD/2. 4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal in question for 3.3-V signaling levels. 5. Input timings are measured at the pin. 6. The value of tLBOTOT is the measurement of the minimum time between the negation of LALE and any change in LAD. 7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 46 Freescale Semiconductor
Local Bus
Internal Launch/Capture Clock tLBKHKT LCLK[n] tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1
tLBIVKL2 Input Signal: LGTA tLBIXKL2
LUPWAIT tLBKLOV1 Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] tLBKLOV2 Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKLOV3 Output (Address) Signal: LAD[0:31] tLBOTOT LALE tLBKLOX2 tLBKLOX1 tLBKLOZ1
tLBKLOZ2
Figure 25. Local Bus Signals (PLL Bypass Mode)
NOTE In PLL bypass mode, LCLK[n] is the inverted version of the internal clock with the delay of tLBKHKT. In this mode, signals are launched at the rising edge of the internal clock and are captured at falling edge of the internal clock withe the exception of LGTA/LUPWAIT (which is captured on the rising edge of the internal clock).
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 47
Local Bus
LSYNC_IN
T1 T3 tLBKHOV1 tLBKHOZ1
GPCM Mode Output Signals: LCS[0:7]/LWE
GPCM Mode Input Signal: LGTA tLBIVKH2 tLBIXKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 tLBIXKH1 tLBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBKHOZ1
Input Signals: LAD[0:31]/LDP[0:3]
Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Enabled)
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 48 Freescale Semiconductor
Local Bus
Internal Launch/Capture Clock T1 T3
LCLK
tLBKLOV1 GPCM Mode Output Signals: LCS[0:7]/LWE
tLBKLOX1
tLBKLOZ1 GPCM Mode Input Signal: LGTA tLBIVKL2 tLBIXKL2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode)
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 49
Local Bus
LSYNC_IN
T1 T2 T3 T4 tLBKHOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBKHOZ1
GPCM Mode Input Signal: LGTA tLBIVKH2 tLBIXKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 tLBIXKH1
Figure 28. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Enabled)
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 50 Freescale Semiconductor
Programmable Interrupt Controller
Internal Launch/Capture Clock T1 T2 T3 T4
LCLK
tLBKLOV1 GPCM Mode Output Signals: LCS[0:7]/LWE
tLBKLOX1
tLBKLOZ1 GPCM Mode Input Signal: LGTA tLBIVKL2 tLBIXKL2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 29. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Bypass Mode)
11 Programmable Interrupt Controller
In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods).
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 51
JTAG
12 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8533E.
12.1
JTAG DC Electrical Characteristics
Table 44. JTAG DC Electrical Characteristics
Parameter Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- 2.4 -- Max OVDD + 0.3 0.8 5 -- 0.4 Unit V V A V V Notes -- -- 1 -- --
Table 44 provides the DC electrical characteristics for the JTAG interface.
High-level input voltage Low-level input voltage Input current (OVIN = 0 V or OVIN = OVDD) High-level output voltage (OVDD = min, IOH = -2 mA) Low-level output voltage (OVDD = min, IOL = 2 mA) Note: 1. Note that the symbol VIN, in this case, represents the OV IN.
12.2
JTAG AC Electrical Specifications
Table 45. JTAG AC Timing Specifications (Independent of SYSCLK)1
Table 45 provides the JTAG AC timing specifications as defined in Figure 30 through Figure 33.
At recommended operating conditions (see Table 3).
Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO
Symbol2 fJTG tJTG tJTKHKL tJTGR & tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV
Min 0 30 15 0 25 4 0
Max 33.3 -- -- 2 -- -- --
Unit MHz ns ns ns ns ns
Notes -- -- -- -- 3 4
ns 20 25 -- -- ns 4 4 20 25
4
5
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 52 Freescale Semiconductor
JTAG
Table 45. JTAG AC Timing Specifications (Independent of SYSCLK)1 (continued)
At recommended operating conditions (see Table 3).
Parameter Output hold times: Boundary-scan data TDO JTAG external clock to output high impedance: Boundary-scan data TDO
Symbol2
Min
Max
Unit ns
Notes 5
tJTKLDX tJTKLOX tJTKLDZ tJTKLOZ
4 4
-- -- ns 5
3 3
19 9
Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- load (see Figure 30). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK.
Figure 30 provides the AC test load for TDO and the boundary-scan outputs.
Output Z0 = 50 OVDD/2
RL = 50
Figure 30. AC Test Load for the JTAG Interface
Figure 31 provides the JTAG clock input timing diagram.
JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (OVDD/2) VM VM tJTGR tJTGF
Figure 31. JTAG Clock Input Timing Diagram
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 53
I2C
Figure 32 provides the TRST timing diagram.
TRST VM tTRST VM = Midpoint Voltage (OVDD/2) VM
Figure 32. TRST Timing Diagram
Figure 33 provides the boundary-scan timing diagram.
JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM
Figure 33. Boundary-Scan Timing Diagram
13 I2C
This section describes the DC and AC electrical characteristics for the I2C interfaces of the MPC8533E.
13.1
I2C DC Electrical Characteristics
Table 46. I2C DC Electrical Characteristics
Table 46 provides the DC electrical characteristics for the I2C interfaces.
At recommended operating conditions with OVDD of 3.3 V 5%.
Parameter Input high voltage level Input low voltage level Low level output voltage Pulse width of spikes which must be suppressed by the input filter
Symbol VIH VIL VOL tI2KHKL
Min 0.7 x OV DD -0.3 0 0
Max OVDD + 0.3 0.3 x OV DD 0.2 x OV DD 50
Unit V V V ns
Notes -- -- 1 2
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 54 Freescale Semiconductor
I2C
Table 46. I2C DC Electrical Characteristics (continued)
At recommended operating conditions with OVDD of 3.3 V 5%.
Parameter Input current each I/O pin (input voltage is between 0.1 x OVDD and 0.9 x OVDD(max) Capacitance for each I/O pin
Symbol II CI
Min -10 --
Max 10 10
Unit A pF
Notes 3 --
Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. Refer to the MPC8533E PowerQUICC III Integrated Communications Host Processor Reference Manual for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
13.2
I2C AC Electrical Specifications
Table 47. I2C AC Electrical Specifications
Table 47 provides the AC timing parameters for the I2C interfaces.
All values refer to VIH (min) and VIL (max) levels (see Table 46).
Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: CBUS compatible masters I2C bus devices Data output delay time Set-up time for STOP condition Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis)
Symbol1 fI2C tI2CL tI2CH tI2SVKH tI2SXKL tI2DVKH tI2DXKL
Min 0 1.3 0.6 0.6 0.6 100 -- 0
Max 400 -- -- -- -- -- -- -- 0.9 -- 300 300 -- --
Unit kHz s s s s ns s
Notes -- -- -- -- -- -- 2
tI2OVKL tI2PVKH tI2CR tI2CF tI2KHDX VNL
-- 0.6 20 + 0.1 C b 20 + 0.1 C b 1.3 0.1 x OV DD
3 s ns ns s V -- 4 4 -- --
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 55
I2C
Table 47. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 46).
Parameter Noise margin at the HIGH level for each connected device (including hysteresis)
Symbol1 VNH
Min 0.2 x OV DD
Max --
Unit V
Notes --
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. The MPC8533E provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF.
Figure 34 provides the AC test load for the I2C.
Output Z0 = 50 RL = 50 OVDD/2
Figure 34. I2C AC Test Load
Figure 35 shows the AC timing diagram for the I2C bus.
SDA tI2CF tI2CL SCL tI2SXKL S tI2CH tI2DXKL,tI2OXKL tI2SVKH Sr tI2PVKH P S tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF
Figure 35. I2C Bus AC Timing Diagram
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 56 Freescale Semiconductor
GPIO
14 GPIO
This section describes the DC and AC electrical specifications for the GPIO interface of the MPC8533E.
14.1
GPIO DC Electrical Characteristics
Table 48. GPIO DC Electrical Characteristics
Parameter Symbol VIH VIL IIN VOH VOL Min 2 - 0.3 -- 2.4 -- Max OVDD + 0.3 0.8 5 -- 0.4 Unit V V A V V Notes -- -- 1 -- --
Table 48 provides the DC electrical characteristics for the GPIO interface.
High-level input voltage Low-level input voltage Input current (V IN = 0 V or VIN = VDD) High-level output voltage (OVDD = mn, IOH = -2 mA) Low-level output voltage (OVDD = min, IOL = 2 mA)
Note: 1. Note that the symbol VIN, in this case, represents the OV IN symbol referenced in Table 1 and Table 2.
14.2
GPIO AC Electrical Specifications
Table 49. GPIO Input AC Timing Specifications
Parameter Symbol tPIWID Typ 20 Unit ns Notes 1
Table 49 provides the GPIO input and output AC timing specifications.
GPIO inputs--minimum pulse width
Note: 1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.
Figure 36 provides the AC test load for the GPIO.
Output Z0 = 50 RL = 50 OVDD/2
Figure 36. GPIO AC Test Load
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 57
PCI
15 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8533E.
15.1
PCI DC Electrical Characteristics
Table 50. PCI DC Electrical Characteristics 1
Parameter Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- 2.4 -- Max OVDD + 0.3 0.8 5 -- 0.4 Unit V V A V V Notes -- -- 2 -- --
Table 50 provides the DC electrical characteristics for the PCI interface.
High-level input voltage Low-level input voltage Input current (V IN = 0 V or VIN = VDD) High-level output voltage (OVDD = min, IOH = -2mA) Low-level output voltage (OVDD = min, IOL = 2 mA)
Notes: 1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications. 2. Note that the symbol VIN, in this case, represents the OV IN symbol referenced in Table 1 and Table 2.
15.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is used as the PCI input clock. Table 51 provides the PCI AC timing specifications at 66 MHz.
Table 51. PCI AC Timing Specifications at 66 MHz
Parameter SYSCLK to output valid Output hold from SYSCLK SYSCLK to output high impedance Input setup to SYSCLK Input hold from SYSCLK REQ64 to HRESET9 setup time HRESET to REQ64 hold time HRESET high to first FRAME assertion Rise time (20%-80%) Symbol1 tPCKHOV tPCKHOX tPCKHOZ tPCIVKH tPCIXKH tPCRVRH tPCRHRX tPCRHFV tPCICLK Min -- 2.0 -- 3.7 0.5 10 x tSYS 0 10 0.6 Max 7.4 -- 14 -- -- -- 50 -- 2.1 Unit ns ns ns ns ns clocks ns clocks ns Notes 2, 3 2 2, 4 2, 5 2, 5 6, 7 7 8 --
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 58 Freescale Semiconductor
PCI
Table 51. PCI AC Timing Specifications at 66 MHz (continued)
Parameter Fall time (20%-80%) Symbol1 tPCICLK Min 0.6 Max 2.1 Unit ns Notes --
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications. 3. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 x OVDD of the signal in question for 3.3-V PCI signaling levels. 4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. Input timings are measured at the pin. 6. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values see Section 19, "Clocking." 7. The setup and hold time is with respect to the rising edge of HRESET. 8. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus Specifications. 9. The reset assertion timing requirement for HRESET is 100 s.
Figure 37 provides the AC test load for PCI.
Output Z0 = 1 K RL = 50 OVDD/2
Figure 37. PCI AC Test Load
Figure 38 shows the PCI input AC timing conditions.
CLK tPCIVKH tPCIXKH Input
Figure 38. PCI Input AC Timing Measurement Conditions
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 59
High-Speed Serial Interfaces (HSSI)
Figure 39 shows the PCI output AC timing conditions.
CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output
Figure 39. PCI Output AC Timing Measurement Condition
16 High-Speed Serial Interfaces (HSSI)
The MPC8533E features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications.Both SerDes1 and SerDes2 can be used for PCI Express data transfers application.This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes Reference Clocks. The SerDes data lane's transmitter and receiver reference circuits are also shown.
16.1
Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. Figure 40 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each signal swings between A Volts and B Volts where A > B. Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. 1. Single-Ended Swing The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and SDn_RX each have a peak-to-peak swing of A - B Volts. This is also referred as each signal wire's Single-Ended Swing. 2. Differential Output Voltage, VOD (or Differential Output Swing): The Differential Output Voltage (or Swing) of the transmitter, VOD, is defined as the difference of the two complimentary output voltages: VSDn_TX - VSDn_TX. The VOD value can be either positive or negative.
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High-Speed Serial Interfaces (HSSI)
3. Differential Input Voltage, VID (or Differential Input Swing): The Differential Input Voltage (or Swing) of the receiver, VID, is defined as the difference of the two complimentary input voltages: VSDn_RX - VSDn_RX. The VID value can be either positive or negative. 4. Differential Peak Voltage, VDIFFp The peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak Voltage, VDIFFp = |A - B| Volts. 5. Differential Peak-to-Peak, VDIFFp-p Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to -(A - B) Volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak-to-Peak Voltage, VDIFFp-p = 2*VDIFFp = 2 * |(A - B)| Volts, which is twice of differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage can also be calculated as VTX-DIFFp-p = 2*|VOD|. 6. Differential Waveform The differential waveform is constructed by subtracting the inverting signal (SDn_TX, for example) from the non-inverting signal (SDn_TX, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to Figure 40 as an example for differential waveform. 7. Common Mode Voltage, Vcm The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = VSDn_TX + VSDn_TX = (A + B) / 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component's output to the other's input. Sometimes, it may be even different between the receiver input and driver output circuits within the same component. It is also referred as the DC offset in some occasions.
SDn_TX or SDn_RX A Volts
Vcm = (A + B) / 2 SDn_TX or SDn_RX B Volts
Differential Swing, VID or VOD = A - B Differential Peak Voltage, VDIFFp = |A - B| Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)
Figure 40. Differential Voltage Definitions for Transmitter or Receiver
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High-Speed Serial Interfaces (HSSI)
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output's differential swing (VOD) has the same amplitude as each signal's single-ended swing. The differential output signal ranges between 500 mV and -500 mV, in other words, VOD is 500 mV in one phase and -500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
16.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and SD1_REF_CLK for PCI Express1 PCI Express2. SD2_REF_CLK and SD2_REF_CLK for the PCI Express3. The following sections describe the SerDes reference clock requirements and some application information.
16.2.1
SerDes Reference Clock Receiver Characteristics
Figure 41 shows a receiver reference diagram of the SerDes reference clocks. * The supply voltage requirements for XVDD_SRDS2 are specified in Table 1 and Table 2. * SerDes reference clock receiver reference circuit structure -- The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 41. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50- termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling. -- The external reference clock driver must be able to drive this termination. -- The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and single-ended mode description below for further detailed requirements. * The maximum average current requirement that also determines the common mode voltage range: -- When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip. -- This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA (0-0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.
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High-Speed Serial Interfaces (HSSI)
*
-- If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 to SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip. The input amplitude requirement -- This requirement is described in detail in the following sections.
50 SDn_REF_CLK Input Amp SDn_REF_CLK 50
Figure 41. Receiver of SerDes Reference Clocks
16.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8533E SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. * Differential Mode -- The input amplitude of the differential clock must be between 400 and 1600 mV differential peak-peak (or between 200 and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-coupled or AC-coupled connection. -- For external DC-coupled connection, as described in Section 16.2.1, "SerDes Reference Clock Receiver Characteristics," the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 and 400 mV. Figure 42 shows the SerDes reference clock input requirement for DC-coupled connection scheme. -- For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (SGND_SRDSn). Figure 43 shows the SerDes reference clock input requirement for AC-coupled connection scheme.
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High-Speed Serial Interfaces (HSSI)
*
Single-ended Mode -- The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be between 400 and 800 mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or tied to ground. -- The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 44 shows the SerDes reference clock input requirement for single-ended signaling mode. -- To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.
SDn_REF_CLK 200 mV < Input Amplitude or Differential Peak < 800 mV Vmax < 800 mV
100 mV < Vcm < 400 mV
SDn_REF_CLK
Vmin > 0 V
Figure 42. Differential Reference Clock Input DC Requirements (External DC-Coupled)
200 mV < Input Amplitude or Differential Peak < 800 mV SDn_REF_CLK Vmax < Vcm + 400 mV
Vcm
SDn_REF_CLK
Vmin > Vcm - 400 mV
Figure 43. Differential Reference Clock Input DC Requirements (External AC-Coupled)
400 mV < SDn_REF_CLK Input Amplitude < 800 mV
SDn_REF_CLK
0V SDn_REF_CLK
Figure 44. Single-Ended Reference Clock Input DC Requirements
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High-Speed Serial Interfaces (HSSI)
16.2.3
Interfacing With Other Differential Signaling Levels
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are HCSL (high-speed current steering logic) compatible DC-coupled. Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be used but may need to be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection. LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. NOTE Figure 45 through Figure 48 are for conceptual reference only. Due to the fact that clock driver chip's internal structure, output impedance and termination requirements are different between various clock driver chip manufacturers, it is very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the MPC8533E SerDes reference clock receiver requirement provided in this document. Figure 45 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8533E SerDes reference clock input's DC requirement.
MPC8533EMP
HCSL CLK Driver Chip
CLK_Out 33 SDn_REF_CLK 50
Clock Driver 33 CLK_Out
100 differential PWB trace
SerDes Refer. CLK Receiver
SDn_REF_CLK
50
Total 50 . Assume clock driver's output impedance is about 16 .
Clock driver vendor dependent source termination resistor
Figure 45. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
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High-Speed Serial Interfaces (HSSI)
Figure 46 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver's common mode voltage is higher than the MPC8533E SerDes reference clock input's allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50- termination resistor. It also assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external component.
MPC8533E
LVDS CLK Driver Chip
CLK_Out 10 nF SDn_REF_CLK 50
Clock Driver
100 differential PWB trace
SerDes Refer. CLK Receiver
CLK_Out
10 nF
SDn_REF_CLK
50
Figure 46. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
Figure 47 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL driver's DC levels (both common mode voltages and output swing) are incompatible with MPC8533E SerDes reference clock input's DC requirement, AC-coupling has to be used. Figure 47 assumes that the LVPECL clock driver's output impedance is 50 . R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140 to 240 depending on clock driver vendor's requirement. R2 is used together with the SerDes reference clock receiver's 50- termination resistor to attenuate the LVPECL output's differential peak level such that it meets the MPC8533E SerDes reference clock's differential input amplitude requirement (between 200 and 800 mV differential peak). For example, if the LVPECL output's differential peak is 900 mV and the desired SerDes reference clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 . Please
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High-Speed Serial Interfaces (HSSI)
consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip.
LVPECL CLK Driver Chip
CLK_Out R2 10nF SDn_REF_CLK MPC8533E 50
Clock Driver
R1
100 differential PWB trace R2 10nF SDn_REF_CLK
SerDes Refer. CLK Receiver
CLK_Out R1
50
Figure 47. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
Figure 48 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8533E SerDes reference clock input's DC requirement.
Single-Ended CLK Driver Chip
Total 50 . Assume clock driver's output impedance is about 16 . 33 CLK_Out SDn_REF_CLK 50 MPC8533E
Clock Driver
100 differential PWB trace
SerDes Refer. CLK Receiver
50
SDn_REF_CLK
50
Figure 48. Single-Ended Connection (Reference Only)
16.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
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High-Speed Serial Interfaces (HSSI)
occurs in the 1-15 MHz range. The source impedance of the clock driver should be 50 to match the transmission line and reduce reflections which are a source of noise to the system. Table 52 describes some AC parameters common to SGMII, and PCI Express protocols.
Table 52. SerDes Reference Clock Common AC Parameters
Parameter Rising Edge Rate Falling Edge Rate Differential Input High Voltage Differential Input Low Voltage Rising edge rate (SDn_REF_CLK) to falling edge rate (SDn_REF_CLK) matching Symbol Rise Edge Rate Fall Edge Rate VIH VIL Rise-Fall Matching Min 1.0 1.0 +200 -- -- Max 4.0 4.0 -- -200 20 Unit V/ns V/ns mV mV % Notes 2, 3 2, 3 2 2 1, 4
Notes: 1. Measurment taken from single ended waveform. 2. Measurment taken from differential waveform. 3. Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 49. 4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge rate of SDn_REF_CLK should be compared to the fall edge rate of SDn_REF_CLK, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 50.
Rise Edge Rage
Fall Edge Rate
VIH = +200 mV 0.0 V VIL = -200 mV SDn_REF_CLK minus SDn_REF_CLK
Figure 49. Differential Measurement Points for Rise and Fall Time
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 68 Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
SDn_REF_CLK
SDn_REF_CLK VCROSS MEDIAN + 100 mV
TFALL
TRISE
VCROSS MEDIAN
VCROSS MEDIAN VCROSS MEDIAN - 100 mV
SDn_REF_CLK
SDn_REF_CLK
Figure 50. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol based on application usage. Refer to the following sections for detailed information: * Section 17.2, "AC Requirements for PCI Express SerDes Clocks"
16.2.4.1
Spread Spectrum Clock
SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to -0.5% spreading at 30-33 kHz rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended modulation should be used. SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock source.
16.3
SerDes Transmitter and Receiver Reference Circuits
SD1_TXn or 50 SD2_TXn SD1_RXn or SD2_RXn 50 Transmitter 50 SD1_TXn or SD2_TXn SD1_RXn or SD2_RXn 50
Figure 51 shows the reference circuits for SerDes data lane's transmitter and receiver.
Receiver
Figure 51. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in the section below (PCI Express) in this document based on the application usage: * Section 17, "PCI Express" Please note that external AC Coupling capacitor is required for the above serial transmission protocols with the capacitor value defined in specification of each protocol section.
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17 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8533E.
17.1
DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK
For more information, see Section 16.2, "SerDes Reference Clocks."
17.2
AC Requirements for PCI Express SerDes Clocks
Table 53. SD_REF_CLK and SD_REF_CLK AC Requirements
Table 53 provides the AC requirements for the PCI Express SerDes clocks.
Symbol2 tREF tREFCJ tREFPJ
Parameter Description REFCLK cycle time REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles Phase jitter. Deviation in edge location with respect to mean edge location
Min -- -- -50
Typ 10 -- --
Max -- 100 50
Units ns ps ps
Notes 1 -- --
Notes: 1. Typical based on PCI Express Specification 2.0. 2. Guaranteed by characterization.
17.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a 300 ppm tolerance.
17.4
Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the transport and data link layer please refer to the PCI Express Base Specification. Rev. 1.0a.
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17.4.1
Differential Transmitter (TX) Output
Table 54 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the component pins.
Table 54. Differential Transmitter (TX) Output Specifications
Symbol UI Parameter Unit interval Min 399.88 Nom 400 Max 400.12 Unit ps Comments Each UI is 400 ps 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note 1. VTX-DIFFp-p = 2*|VTX-D+ - VTX-D-|. See Note 2. Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. See Note 2. The maximum transmitter jitter can be derived as TTX-MAX-JITTER = 1 - TTX-EYE = 0.3 UI. See Notes 2 and 3. Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. See Notes 2 and 3. See Notes 2 and 5. VTX-CM-ACp = RMS(|VTXD+ - VTXD-|/2 - VTX-CM-DC) VTX-CM-DC = DC(avg) of |VTX-D+ - VTX-D-|/2 See Note 2. |VTX-CM-DC (during LO) - VTX-CM-Idle-DC (During Electrical Idle)|<= 100 mV VTX-CM-DC = DC(avg) of |VTX-D+ - VTX-D-|/2 [LO] VTX-CM-Idle-DC = DC(avg) of |V TX-D+ - VTX-D-|/2 [Electrical Idle] See Note 2. |VTX-CM-DC-D+ - VTX-CM-DC-D-| <= 25 mV VTX-CM-DC-D+ = DC(avg) of |V TX-D+| VTX-CM-DC-D- = DC(avg) of |V TX-D-| See Note 2.
VTX-DIFFp-p VTX-DE-RATIO
Differential peak-topeak output voltage De- emphasized differential output voltage (ratio) Minimum TX eye width
0.8 -3.0
-- -3.5
1.2 -4.0
V dB
TTX-EYE
0.70
--
--
UI
TTX-EYE-MEDIAN-toMAX-JITTER
Maximum time between the jitter median and maximum deviation from the median.
--
--
0.15
UI
TTX-RISE, TTX-FALL VTX-CM-ACp
D+/D- TX output rise/fall time RMS AC peak common mode output voltage
0.125 --
-- --
-- 20
UI mV
VTX-CM-DC-ACTIVEIDLE-DELTA
Absolute delta of DC common mode voltage during LO and electrical idle
0
--
100
mV
VTX-CM-DC-LINE-DELTA
Absolute delta of DC common mode between D+ and D-
0
--
25
mV
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Table 54. Differential Transmitter (TX) Output Specifications (continued)
Symbol VTX-IDLE-DIFFp Parameter Electrical idle differential peak output voltage Amount of voltage change allowed during receiver detection TX DC common mode voltage TX short circuit current limit Minimum time spent in electrical idle Min 0 Nom -- Max 20 Unit mV Comments VTX-IDLE-DIFFp = |VTX-IDLE-D+ - VTX-IDLE-D-| <= 20 mV See Note 2. The total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. See Note 6. The allowed DC common mode voltage under any conditions. See Note 6. The total current the transmitter can provide when shorted to its ground. Minimum time a transmitter must be in electrical idle utilized by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set. After sending an electrical idle ordered set, the transmitter must meet all electrical idle specifications within this time. This is considered a debounce time for the transmitter to meet electrical idle after transitioning from LO. Maximum time to meet all TX specifications when transitioning from electrical idle to sending differential data. This is considered a debounce time for the TX to meet all TX specifications after leaving electrical idle. Measured over 50 MHz to 1.25 GHz. See Note 4. Measured over 50 MHz to 1.25 GHz. See Note 4. TX DC differential mode low impedance. Required TX D+ as well as D- DC Impedance during all states. Static skew between any two transmitter lanes within a single link. All transmitters shall be AC coupled. The AC coupling is required either within the media or within the transmitting component itself.
VTX-RCV-DETECT
--
--
600
mV
VTX-DC-CM ITX-SHORT TTX-IDLE-MIN
0 -- 50
-- -- --
3.6 90 --
V mA UI
TTX-IDLE-SET-TO-IDLE
Maximum time to transition to a valid electrical idle after sending an electrical Idle ordered set Maximum time to transition to valid TX specifications after leaving an electrical idle condition Differential return loss Common mode return loss DC differential TX impedance Transmitter DC impedance Lane-to-lane output skew AC coupling capacitor
--
--
20
UI
TTX-IDLE-TO-DIFF-DATA
--
--
20
UI
RLTX-DIFF RLTX-CM ZTX-DIFF-DC ZTX-DC LTX-SKEW CTX
12 6 80 40 -- 75
-- -- 100 -- -- --
-- -- 120 -- 500 + 2 UI 200
dB dB ps nF
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Table 54. Differential Transmitter (TX) Output Specifications (continued)
Symbol Tcrosslink Parameter Crosslink random timeout Min 0 Nom -- Max 1 Unit ms Comments This random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. See Note 7.
Notes: 1. No test load is necessarily associated with this value. 2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 54 and measured over any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 52.) 3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements is 50 to ground for both the D+ and D- line (that is, as measured by a vector network analyzer with 50- probes--see Figure 54.) Note that the series capacitors CTX is optional for the return loss measurement. 5. Measured between 20%-80% at transmitter package pins into a test load as shown in Figure 54 for both V TX-D+ and VTX-D- . 6. See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a. 7. See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.
17.4.2
Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 52 is specified using the passive compliance/test measurement load (see Figure 54) in place of any real PCI Express interconnect +RX component. There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. NOTE It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits).
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VRX-DIFF = 0 mV (D+ D- Crossing Point)
[Transition Bit] VTX-DIFFp-p-MIN = 800 mV
VTX-DIFF = 0 mV (D+ D- Crossing Point)
[De-Emphasized Bit] 566 mV (3 dB ) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB )
0.07 UI = UI - 0.3 UI (JTX-TOTAL-MAX) [Transition Bit] VTX-DIFFp-p-MIN = 800 mV
Figure 52. Minimum Transmitter Timing and Voltage Output Compliance Specifications
17.4.3
Differential Receiver (RX) Input Specifications
Table 55 defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the component pins.
Table 55. Differential Receiver (RX) Input Specifications
Symbol UI Parameter Unit interval Min 399.88 Nom 400 Max 400.12 Units ps Comments Each UI is 400 ps 300 ppm. UI does not account for spread spectrum clock dictated variations. See Note 1. VRX-DIFFp-p = 2*|VRX-D+ - VRX-D-| See Note 2. The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as TRX-MAX-JITTER = 1 - TRX-EYE = 0.6 UI. See Notes 2 and 3.
VRX-DIFFp-p TRX-EYE
Differential peak-topeak input voltage Minimum receiver eye width
0.175 0.4
-- --
1.200 --
V UI
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Table 55. Differential Receiver (RX) Input Specifications (continued)
Symbol Parameter Min -- Nom -- Max 0.3 Units UI Comments Jitter is defined as the measurement variation of the crossing points (V RX-DIFFp-p = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. See Notes 2, 3, and 7. VRX-CM-ACp = |VRXD+ - VRXD-|/2 - VRX-CM-DC VRX-CM-DC = DC(avg) of |VRX-D+ - VRX-D-|/2 See Note 2. Measured over 50 MHz to 1.25 GHz with the D+ and D- lines biased at +300 and -300 mV, respectively. See Note 4. Measured over 50 MHz to 1.25 GHz with the D+ and D- lines biased at 0 V. See Note 4. RX DC differential mode impedance. See Note 5. Required RX D+ as well as D- DC impedance (50 20% tolerance). See Notes 2 and 5. Required RX D+ as well as D- DC impedance when the receiver terminations do not have power. See Note 6. VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+ - VRX-D-| Measured at the package pins of the receiver. An unexpected electrical idle (VRX-DIFFp-p < V RX-IDLE-DET-DIFFp-p) must be recognized no longer than TRX-IDLE-DET-DIFF-ENTERING to signal an unexpected idle condition.
-JITTER
TRX-EYE-MEDIAN-to-MAX Maximum time between the jitter median and maximum deviation from the median
VRX-CM-ACp
AC peak common mode input voltage
--
--
150
mV
RLRX-DIFF
Differential return loss Common mode return loss DC differential input impedance DC input impedance
15
--
--
dB
RLRX-CM ZRX-DIFF-DC ZRX-DC
6 80 40
-- 100 50
-- 120 60
dB
ZRX-HIGH-IMP-DC
Powered down DC input impedance Electrical idle detect threshold
200 k
--
--
VRX-IDLE-DET-DIFFp-p
65
--
175
mV
TRX-IDLE-DET-DIFFENTERTIME
Unexpected electrical idle enter detect threshold integration time
--
--
10
ms
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 75
PCI Express
Table 55. Differential Receiver (RX) Input Specifications (continued)
Symbol LTX-SKEW Parameter Total skew Min -- Nom -- Max 20 Units ns Comments Skew across all lanes on a link. This includes variation in the length of SKP ordered set (for example, COM and one to five symbols) at the RX as well as any delay differences arising from the interconnect itself.
Notes: 1. No test load is necessarily associated with this value. 2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 54 should be used as the RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 53). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 4. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to 300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 to ground for both the D+ and D- line (that is, as measured by a vector network analyzer with 50- probes, see Figure 54). Note that the series capacitors CTX is optional for the return loss measurement. 5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5-ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 6. The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the RX ground. 7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data.
17.5
Receiver Compliance Eye Diagrams
The RX eye diagram in Figure 53 is specified using the passive compliance/test measurement load (see Figure 54) in place of any real PCI Express RX component. In general, the minimum receiver eye diagram measured with the compliance/test measurement load (see Figure 54) will be larger than the minimum receiver eye diagram measured over a range of systems at the input receiver of any real PCI Express component. The degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI Express component to vary in impedance from the compliance/test measurement load. The input receiver eye diagram is implementation specific and is not specified. RX component designer should provide additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in Figure 53) expected at the input receiver based on some adequate combination of system simulations and the return loss measured looking into the RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 76 Freescale Semiconductor
PCI Express
The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. NOTE The reference impedance for return loss measurements is 50 to ground for both the D+ and D- line (that is, as measured by a vector network analyzer with 50- probes, see Figure 53). Note that the series capacitors, CTX, are optional for the return loss measurement.
VRX-DIFF = 0 mV (D+ D- Crossing Point) VRX-DIFF = 0 mV (D+ D- Crossing Point)
VRX-DIFFp-p-MIN > 175 mV
0.4 UI = TRX-EYE-MIN
Figure 53. Minimum Receiver Eye Timing and Voltage Compliance Specification
17.5.1
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in Figure 54. NOTE The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D- not being exactly matched in length at the package pin boundary.
D+ Package Pin TX Silicon + Package D- Package Pin C = CTX R = 50 R = 50
C = CTX
Figure 54. Compliance Test/Measurement Load
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 77
Package Description
18 Package Description
This section details package parameters, pin assignments, and dimensions.
18.1
Package Parameters for the MPC8533E FC-PBGA
Table 56. Package Parameters
Parameter Package outline Interconnects Ball pitch Ball diameter (typical) Solder ball (Pb-free) Note: 1. (FC-PBGA) without a lid. PBGA1 29 mm x 29 mm 783 1 mm 0.6 mm 96.5% Sn 3.5% Ag
The package parameters for flip chip plastic ball grid array (FC-PBGA) are provided in Table 56.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 78 Freescale Semiconductor
Package Description
18.2
Mechanical Dimensions of the MPC8533E FC-PBGA
Figure 55 shows the mechanical dimensions and bottom surface nomenclature of the MPC8533E, 783 FC-PBGA package without a lid.
Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. 6. Capacitors may not be present on all parts. Care must be taken not to short exposed metal capacitor pads. 7. All dimensions are symmetric across the package center lines, unless dimensioned otherwise.
Figure 55. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8533E FC-PBGA without a Lid
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 79
Package Description
18.3
Pinout Listings
NOTE The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails for the eTSEC blocks and to ease the port of existing PowerQUICC III software. NOTE The DMA_DACK[0:1] and TEST_SEL pins must be set to a proper state during POR configuration. Please refer to Table 57 for more details.
Table 57 provides the pinout listing for the MPC8533E 783 FC-PBGA package.
Table 57. MPC8533E Pinout Listing
Signal Package Pin Number PCI PCI1_AD[31:0] AE8, AD8, AF8, AH12, AG12, AB9, AC9, AE9, AD10, AE10, AC11, AB11, AB12, AC12, AF12, AE11, Y14, AE15, AC15, AB15, AA15, AD16, Y15, AB16, AF18, AE18, AC17, AE19, AD19, AB17, AB18, AA16 AC10, AE12, AA14, AD17 AE7, AG11,AH11, AC8 AE6 AF13 AB14 AE14 AC14 AA13 AD13 AF9, AG10, AH10, AD6 AB8 AH26 AC13 AD12 AG6 I/O OV DD -- Pin Type Power Supply Notes
PCI1_C_BE[3:0] PCI1_GNT[4:1] PCI1_GNT0 PCI1_IRDY PCI1_PAR PCI1_PERR PCI1_SERR PCI1_STOP PCI1_TRDY PCI1_REQ[4:1] PCI1_REQ0 PCI1_CLK PCI1_DEVSEL PCI1_FRAME PCI1_IDSEL
I/O O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I/O I
OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD
-- 4, 8, 24 -- 2 -- 2 2 2 2 -- -- -- 2 2 --
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 80 Freescale Semiconductor
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Signal Package Pin Number DDR SDRAM Memory Interface MDQ[0:63] A26, B26, C22, D21, D25, B25, D22, E21, A24, A23, B20, A20, A25, B24, B21, A21, E19, D19, E16, C16, F19, F18, F17, D16, B18, A18, A15, B14, B19, A19, A16, B15, D1, F3, G1, H2, E4, G5, H3, J4, B2, C3, F2, G2, A2, B3, E1, F1, L5, L4,N3, P3, J3, K4, N4, P4, J1, K1, P1, R1, J2, K2, N1, R2 G12, D14, F11, C11, G14, F14,C13, D12 C25, B23, D18, B17, G4, C2, L3, L2, F13 D24, B22, C18, A17, J5, C1, M4, M2, E13 C23, A22, E17, B16, K5, D2, M3, P2, D13 B7, G8, C8, A10, D9, C10, A11, F9, E9, B12, A5, A12, D11, F7, E10, F10 A4, B5, B13 B4 E7 C5 H10, K10, G10, H9 D3, H6, C4, G6 A9, J11, J6, A8, J13, H8 B9, H11, K6, B8, H13, J8 E5, H7, E6, F6 H15, K15 A13 A6 Local Bus Controller Interface LAD[0:31] K22, L21, L22, K23, K24, L24, L25, K25, L28, L27, K28, K27, J28, H28, H27, G27, G26, F28, F26, F25, E28, E27, E26, F24, E24, C26, G24, E23, G23, F22, G22, G21 K26, G28, B27, E25 L19 K16, K17, H17,G17 K18, G19, H19, H20, G16 H16 I/O BVDD 23 I/O GVDD -- Pin Type Power Supply Notes
MECC[0:7] MDM[0:8] MDQS[0:8] MDQS[0:8] MA[0:15] MBA[0:2] MWE MCAS MRAS MCKE[0:3] MCS[0:3] MCK[0:5] MCK[0:5] MODT[0:3] MDIC[0:1] TEST_IN TEST_OUT
I/O O I/O I/O O O O O O O O O O O I/O I O
GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD -- --
-- 21 -- -- -- -- -- -- -- 10 -- -- -- -- 25 27 17
LDP[0:3] LA[27] LA[28:31] LCS[0:4] LCS5/DMA_DREQ2
I/O O O O I/O
BVDD BVDD BVDD BVDD BVDD 4, 8 4, 6, 8 -- 1
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 81
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Signal LCS6/DMA_DACK2 LCS7/DMA_DDONE2 LWE0/LBS0/LSDDQM[0] LWE1/LBS1/LSDDQM[1] LWE2/LBS2/LSDDQM[2] LWE3/LBS3/LSDDQM[3] LALE LBCTL LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/ LPBSE LGPL5 LCKE LCLK[0:2] LSYNC_IN LSYNC_OUT J16 L18 J22 H22 H23 H21 J26 J25 J20 K20 G20 H18 L20 K19 L17 H24, J24, H25 D27 D28 DMA DMA_DACK[0:1] DMA_DREQ[0:1] DMA_DDONE[0:1] Y13, Y12 AA10, AA11 AA7, Y11 Programmable Interrupt Controller UDE MCP IRQ[0:7] IRQ[8] IRQ[9]/DMA_DREQ3 IRQ[10]/DMA_DACK3 IRQ[11]/DMA_DDONE3 IRQ_OUT AH15 AG18 AG22, AF17, AD21, AF19, AG17, AF16, AC23, AC22 AC19 AG20 AE27 AE24 AD14 I I I I I I/O I/O O OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD -- -- -- -- 1 1 1 2 O I O OV DD OV DD OV DD 4, 8, 9 -- -- Package Pin Number Pin Type O O O O O O O O O O O O I/O O O O I O Power Supply BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD Notes 1 1 4, 8 4, 8 4, 8 4, 8 4, 7, 8 4, 7, 8 4, 8 4, 8 4, 7, 8 4, 8 -- 4, 8 -- -- -- --
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 82 Freescale Semiconductor
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Signal Package Pin Number Ethernet Management Interface EC_MDC EC_MDIO AC7 Y9 Gigabit Reference Clock EC_GTX_CLK125 T2 I Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_RXD[7:0] TSEC1_TXD[7:0] TSEC1_COL TSEC1_CRS TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER TSEC1_TX_CLK TSEC1_TX_EN TSEC1_TX_ER U10, U9, T10, T9, U8, T8, T7, T6 T5, U5, V5, V3, V2, V1, U2, U1 R5 T4 T1 V7 U7 R9 V6 U4 T3 I O I I/O O I I I I O O Three-Speed Ethernet Controller (Gigabit Ethernet 3) TSEC3_RXD[7:0] TSEC3_TXD[7:0] TSEC3_COL TSEC3_CRS TSEC3_GTX_CLK TSEC3_RX_CLK TSEC3_RX_DV TSEC3_RX_ER TSEC3_TX_CLK TSEC3_TX_EN TSEC3_TX_ER P11, N11, M11, L11, R8, N10, N9, P10 M7, N7, P7, M8, L7, R6, P6, M6 M9 L9 R7 P9 P8 R11 L10 N6 L8 DUART UART_CTS[0:1] UART_RTS[0:1] AH8, AF6 AG8, AG9 I O OV DD OV DD -- -- I O I I/O O I I I I O O LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD -- 4, 8, 14 -- 16 -- -- -- -- -- 22 4, 8 LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD -- 4, 8, 14 -- 16 -- -- -- 4, 8 -- 22 -- LVDD -- O I/O OV DD OV DD 4, 8, 14 -- Pin Type Power Supply Notes
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 83
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Signal UART_SIN[0:1] UART_SOUT[0:1] AG7, AH6 AH7, AF7 I2 IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA AG21 AH21 AG13 AG14 SerDes 1 SD1_RX[0:7] SD1_RX[0:7] SD1_TX[0:7] SD1_TX[0:7] SD1_PLL_TPD SD1_REF_CLK SD1_REF_CLK SD1_TST_CLK SD1_TST_CLK N28, P26, R28, T26, Y26, AA28, AB26, AC28 N27, P25, R27, T25, Y25, AA27, AB25, AC27 M23, N21, P23, R21, U21, V23, W21, Y23 M22, N20, P22, R20, U20, V22, W20, Y22 V28 U28 U27 T22 T23 SerDes 2 SD2_RX[0] SD2_RX[2] SD2_RX[3] SD2_RX[0] SD2_RX[2] SD2_RX[3] SD2_TX[0] SD2_TX[2] SD2_TX[3] SD2_TX[0] SD2_TX[2] SD2_TX[3] SD2_PLL_TPD SD2_REF_CLK AD25 AD1 AB2 AD26 AC1 AA2 AA21 AC4 AA5 AA20 AB4 Y5 AG3 AE2 I I I I I I O O O O O O O I XVDD XVDD XVDD XVDD XVDD XVDD XVDD XVDD XVDD XVDD XVDD XVDD XVDD XVDD -- 26 26 -- 26 26 -- 17 17 -- 17 17 17 -- I I O O O I I XVDD XVDD XVDD XVDD XVDD XVDD XVDD -- -- -- -- -- -- 17 -- -- -- -- C interface I/O I/O I/O I/O OV DD OV DD OV DD OV DD 20 20 20 20 Package Pin Number Pin Type I O Power Supply OV DD OV DD Notes -- --
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 84 Freescale Semiconductor
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Signal SD2_REF_CLK SD2_TST_CLK SD2_TST_CLK AF2 AG4 AF4 General-Purpose Output GPOUT[0:7] AF22, AH23, AG27, AH25, AF21, AF25, AG26, AF26 General-Purpose Input GPIN[0:7] AH24, AG24, AD23, AE21, AD22, AF23, AG25, AE20 System Control HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT AG16 AG15 AG19 AH5 AA12 Debug TRIG_IN TRIG_OUT/READY/ QUIESCE MSRCID[0:1] MSRCID[2:4] MDVAL CLK_OUT AC5 AB5 Y7, W9 AA9, AB6, AD5 Y8 AE16 Clock RTC SYSCLK AF15 AH16 JTAG TCK TDI TDO TMS TRST AG28 AH28 AF28 AH27 AH22 I I O I I OV DD OV DD OV DD OV DD OV DD -- 11 10 11 11 I I OV DD OV DD -- -- I O O O O O OV DD OV DD OV DD OV DD OV DD OV DD -- 5, 8, 15, 21 4, 5, 8 5, 15, 21 5 10 I O I I O OV DD OV DD OV DD OV DD OV DD -- 21 -- -- 2, 4 I OV DD -- O OV DD -- Package Pin Number Pin Type I -- -- Power Supply XVDD -- -- Notes -- -- --
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 85
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Signal Package Pin Number DFT L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL AC20 AE17 AH19 AH13 Thermal Management TEMP_ANODE TEMP_CATHODE Y3 AA3 Power Management ASLEEP AH17 Power and Ground Signals GND D5, M10, F4, D26, D23, C12, C15, E20, D8, B10, E3, J14, K21, F8, A3, F16, E12, E15, D17, L1, F21, H1, G13, G15, G18, C6, A14, A7, G25, H4, C20, J12, J15, J17, F27, M5, J27, K11, L26, K7, K8, L12, L15, M14, M16, M18, N13, N15, N17, N2, P5, P14, P16, P18, R13, R15, R17, T14, T16, T18, U13, U15, U17, AA8, U6, Y10, AC21, AA17, AC16, V4, AD7, AD18, AE23, AF11, AF14, AG23, AH9, A27, B28, C27 Y16, AB7, AB10, AB13, AC6, AC18, AD9, AD11, AE13, AD15, AD20, AE5, AE22, AF10, AF20, AF24, AF27 R4, U3 -- -- -- O OV DD 8, 15, 21 -- -- -- -- 13 13 I I I I OV DD OV DD OV DD OV DD 18 18 18 3 Pin Type Power Supply Notes
OVDD[1:17]
Power for PCI and other standards (3.3 V) Power for TSEC1 interfaces (2.5 V, 3.3 V) Power for TSEC3 interfaces (2.5 V, 3.3 V) Power for DDR1 and DDR2 DRAM I/O voltage (1.8 V, 2.5 V) Power for local bus (1.8 V, 2.5 V, 3.3 V)
OV DD
--
LVDD[1:2]
LVDD
--
TVDD[1:2]
N8, R10
TVDD
--
GV DD
B1, B11, C7, C9, C14, C17, D4, D6, R3, D15, E2, E8,C24, E18, F5, E14, C21, G3, G7, G9, G11, H5, H12, E22, F15, J10, K3, K12, K14, H14, D20, E11, M1, N5 L23, J18, J19, F20, F23, H26, J21, J23
GVDD
--
BVDD
BVDD
--
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 86 Freescale Semiconductor
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Signal VDD Package Pin Number L16, L14, M13, M15, M17, N12, N14, N16, N18, P13, P15, P17, R12, R14, R16, R18, T13, T15, T17, U12, U14, U16, U18, M27, N25, P28, R24, R26, T24, T27, U25, W24, W26, Y24, Y27, AA25, AB28, AD27 Pin Type Power for core (1.0 V) Core power for SerDes 1 transceivers (1.0 V) Core power for SerDes 2 transceivers (1.0 V) Pad power for SerDes 1 transceivers (1.0 V) Pad power for SerDes 2 transceivers (1.0 V) -- -- -- Power Supply VDD Notes --
SVDD_SRDS
SVDD
--
SVDD_SRDS2
AB1, AC26, AD2, AE26, AG2
SVDD
--
XVDD_SRDS
M21, N23, P20, R22, T20, U23, V21, W22, Y20
XVDD
--
XVDD_SRDS2
Y6, AA6, AA23, AF5, AG5
XVDD
--
XGND_SRDS XGND_SRDS2 SGND_SRDS
M20, M24, N22, P21, R23, T21, U22, V20, W23, Y21 Y4, AA4, AA22, AD4, AE4, AH4 M28, N26, P24, P27, R25, T28, U24, U26, V24, W25, Y28, AA24, AA26, AB24, AB27, AC24, AD28 V27 Y2, AA1, AB3, AC2, AC3, AC25, AD3, AD24, AE3, AE1, AE25, AF3, AH2 AF1 C28
-- -- --
-- -- --
AGND_SRDS SGND_SRDS2 AGND_SRDS2 AVDD_LBIU
SerDes PLL GND -- SerDes PLL GND Power for local bus PLL (1.0 V) Power for PCI PLL (1.0 V) Power for e500 PLL (1.0 V) Power for CCB PLL (1.0 V)
-- -- -- --
-- -- -- 19
AVDD_PCI1
AH20
--
19
AVDD_CORE AVDD_PLAT
AH14 AH18
-- --
19 19
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 87
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Signal AVDD_SRDS W28 Package Pin Number Pin Type Power for SRDSPLL (1.0 V) Power for SRDSPLL (1.0 V) O -- Analog Signals MVREF A28 Reference voltage signal for DDR -- -- -- I I O No Connect Pins NC C19, D7, D10, K13, L6, K9, B6, F12, J7, M19, M25, N19, N24, P19, R19, AB19, T12, W3, M12, W5, P12, T19, W1, W7, L13, U19, W4, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, W2, W6, W8, T11, U11, W12, W13, W14, W15, W16, W17, W18, W19, W27, V25, Y17, Y18, Y19, AA18, AA19, AB20, AB21, AB22, AB23, J9 -- -- -- MVREF -- Power Supply -- Notes 19
AVDD_SRDS2
AG1
--
19
SENSEVDD SENSEVSS
W11 W10
VDD --
12 12
SD1_IMP_CAL_RX SD1_IMP_CAL_TX SD1_PLL_TPA SD2_IMP_CAL_RX SD2_IMP_CAL_TX SD2_PLL_TPA
M26 AE28 V26 AH3 Y1 AH1
200 to GND 100 to GND AVDD_SRDS ANALOG 200 to GND 100 to GND AVDD_SRDS2 ANALOG
-- -- 17 -- -- 17
Notes: 1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as DMA_REQ2. 2. Recommend a weak pull-up resistor (2-10 K) be placed on this pin to OVDD. 3. This pin must always be pulled high. 4. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pull-up or active driver is needed. 5. Treat these pins as no connects (NC) unless using debug address functionality.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 88 Freescale Semiconductor
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Notes
6. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k pull-up or pull-down resistors. See Section 19.2, "CCB/SYSCLK PLL Ratio." 7. The value of LALE, LGPL2, and LBCTL at reset set the e500 core clock to CCB clock PLL ratio. These pins require 4.7-k pull-up or pull-down resistors. See Section 19.3, "e500 Core PLL Ratio." 8. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or because it has other manufacturing test functions. Therefore, this pin will be described as an I/O for boundary scan. 9. For proper state of these signals during reset, these pins can be left without any pull downs, thus relying on the internal pullup to get the values to the require 2'b11. However, if there is any device on the net which might pull down the value of the net at reset, then a pullup is needed. 10. This output is actively driven during reset rather than being three-stated during reset. 11. These JTAG pins have weak internal pull-up P-FETs that are always enabled. 12. These pins are connected to the V DD/GND planes internally and may be used by the core power supply to improve tracking and regulation. 13. Anode and cathode of internal thermal diode. 14. Treat pins AC7, T5, V2, and M7 as spare configuration pins cfg_spare[0:3]. The spare pins are unused POR config pins. It is highly recommended that the customer provide the capability of setting these pins low (that is, pull-down resistor which is not currently stuffed) in order to support new config options should they arise between revisions. 15. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state during reset. 16. This pin is only an output in FIFO mode when used as Rx flow control. 17. Do not connect. 18. These are test signals for factory use only and must be pulled up (100 to 1 k) to OVDD for normal machine operation. 19. Independent supplies derived from board VDD. 20. Recommend a pull-up resistor (1 K~) be placed on this pin to OVDD. 21. The following pins must not be pulled down during power-on reset: HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], and ASLEEP. 22. This pin requires an external 4.7-k pull-down resistor to prevent PHY from seeing a valid transmit enable before it is actively driven. 23. General-purpose POR configuration of user system. 24. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as No Connect or terminated through 2-10 k pull-up resistors with the default of internal arbiter if the address pins are not connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter--through POR config pins--irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is any other PCI device connected on the bus. 25. MDIC0 is grounded through an 18.2- precision 1% resistor and MDIC1 is connected GVDD through an 18.2- precision 1% resistor. These pins are used for automatic calibration of the DDR IOs. 26. Connect to GND. 27.Connect to GND.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 89
Clocking
19 Clocking
This section describes the PLL configuration of the MPC8533E . Note that the platform clock is identical to the core complex bus (CCB) clock.
19.1
Clock Ranges
Table 58 provides the clocking specifications for the processor cores and Table 59 provides the clocking specifications for the memory bus.
Table 58. Processor Core Clocking Specifications
Maximum Processor Core Frequency Characteristic 667 MHz Min e500 core processor frequency 667 Max 667 800 MHz Min 667 Max 800 1000 MHz Min 667 Max 1000 1067 MHz Min 667 Max 1067 MHz 1, 2 Unit Notes
Notes: 1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 19.2, "CCB/SYSCLK PLL Ratio," and Section 19.3, "e500 Core PLL Ratio," for ratio settings. 2. The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
Table 59. Memory Bus Clocking Specifications
Maximum Processor Core Frequency Characteristic 667, 800, 1000, 1067 MHz Min Memory bus clock speed 166 Max 266 MHz 1, 2 Unit Notes
Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 19.2, "CCB/SYSCLK PLL Ratio," and Section 19.3, "e500 Core PLL Ratio," for ratio settings. 2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.
19.2
CCB/SYSCLK PLL Ratio
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform clock. The frequency of the CCB is set using the following reset signals (see Table 60): * SYSCLK input signal * Binary value on LA[28:31] at power up Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note that the DDR data rate is the determining factor in selecting the CCB bus frequency, since the CCB frequency must equal the DDR data rate.
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Clocking
Table 60. CCB Clock Ratio
Binary Value of LA[28:31] Signals 0000 0001 0010 0011 0100 0101 0110 0111 CCB:SYSCLK Ratio 16:1 Reserved Reserved 3:1 4:1 5:1 6:1 Reserved Binary Value of LA[28:31] Signals 1000 1001 1010 1011 1100 1101 1110 1111 CCB:SYSCLK Ratio 8:1 9:1 10:1 Reserved 12:1 Reserved Reserved Reserved
19.3
e500 Core PLL Ratio
Table 61 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is determined by the binary value of LBCTL, LALE, and LGPL2 at power up, as shown in Table 61.
Table 61. e500 Core to CCB Clock Ratio
Binary Value of LBCTL, LALE, LGPL2 Signals 000 001 010 011 Binary Value of LBCTL, LALE, LGPL2 Signals 100 101 110 111
e500 core:CCB Clock Ratio
e500 core:CCB Clock Ratio
4:1 Reserved Reserved 3:2
2:1 5:2 3:1 7:2
19.4
PCI Clocks
For specifications on the PCI_CLK, refer to the PCI 2.2 Local Bus Specifications. The use of PCI_CLK is optional if SYSCLK is in the range of 33-66 MHz. If SYSCLK is outside this range then use of PCI_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 91
Clocking
19.5
Security Controller PLL Ratio
Table 62. SEC Frequency Ratio
Signal Name LWE_B Value (Binary) 0 1 CCB CLK:SEC CLK 2:11 3:12
Table 62 shows the SEC frequency ratio.
Notes: 1. In 2:1 mode the CCB frequency must be operating <= 400 MHz. 2. In 3:1 mode any valid CCB can be used. The 3:1 mode is the default ratio for security block.
19.6
19.6.1
Frequency Options
SYSCLK to Platform Frequency Options
Table 63 shows the expected frequency values for the platform frequency when using a CCB clock to SYSCLK ratio in comparison to the memory bus clock speed.
Table 63. Frequency Options of SYSCLK with Respect to Memory Bus Speeds
CCB to SYSCLK Ratio 33.33 41.66 66.66 SYSCLK (MHz) 83 100 111 133.33
Platform /CCB Frequency (MHz) 2 3 4 5 6 8 9 10 12 16 333 400 533 333 375 417 500 -- 333 400 533 333 415 500 -- 400 500 333 445 -- 400 533
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Thermal
19.6.2
Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed. Refer to Section 4.4, "Platform to FIFO Restrictions," for additional information.
Table 64. FIFO Maximum Speed Restrictions
Platform Speed (MHz) 533 400 Maximum FIFO Speed for Reference Clocks TSECn_TX_CLK, TSECn_RX_CLK (MHz)1 126 94
Note: 1. FIFO speed should be less than 24% of the platform speed.
20 Thermal
This section describes the thermal specifications of the MPC8533E.
20.1
Thermal Characteristics
Table 65. Package Thermal Characteristics
Characteristic JEDEC Board Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) -- -- Symbol RJA RJA RJA RJA RJB RJC Value 26 21 21 17 12 <0.1 Unit C/W C/W C/W C/W C/W C/W Notes 1, 2 1, 2 1, 2 1, 2 3 4
Table 65 provides the package thermal characteristics.
Junction-to-ambient natural convection Junction-to-ambient natural convection Junction-to-ambient (@200 ft/min) Junction-to-ambient (@200 ft/min) Junction-to-board thermal Junction-to-case thermal
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 and JESD51-6 with the board (JESD51-9) horizontal. 3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1C/W.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 93
Thermal
Table 66 provides the thermal resistance with heat sink in open flow.
Table 66. Thermal Resistance with Heat Sink in Open Flow
Heat Sink with Thermal Grease Wakefield 53 x 53 x 25 mm pin fin Wakefield 53 x 53 x 25 mm pin fin Aavid 35 x 31 x 23 mm pin fin Aavid 35 x 31 x 23 mm pin fin Aavid 30 x 30 x 9.4 mm pin fin Aavid 30 x 30 x 9.4 mm pin fin Aavid 43 x 41 x 16.5 mm pin fin Aavid 43 x 41 x 16.5 mm pin fin Air Flow Natural convection 1 m/s Natural convection 1 m/s Natural convection 1 m/s Natural convection 1 m/s Thermal Resistance (C/W) 6.1 3.0 8.1 4.3 11.6 6.7 8.3 4.3
Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The thermal interface material was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease. For system thermal modeling, the MPC8533E thermal model without a lid is shown in Figure 56. The substrate is modeled as a block 29 x 29 x 1.18 mm with an in-plane conductivity of 18.0 W/m*K and a through-plane conductivity of 1.0 W/m*K. The solder balls and air are modeled as a single block 29 x 29 x 0.58 mm with an in-plane conductivity of 0.034 W/m*K and a through plane conductivity of 12.1 W/m*K. The die is modeled as 7.6 x 8.4 mm with a thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed thermal resistance between the die and substrate assuming a conductivity of 6.5 W/m*K in the thickness dimension of 0.07 mm. The die is centered on the substrate. The thermal model uses approximate dimensions to reduce grid. Please refer to Figure 55 for actual dimensions.
20.2
Recommended Thermal Model
Table 67. MPC8533EThermal Model
Conductivity Value Die (7.6 x 8.4 x 0.75mm) Silicon Temperature dependent -- Units
Table 67 shows the MPC8533E thermal model.
Bump/Underfill (7.6 x 8.4 x 0.070 mm) Collapsed Thermal Resistance Kz 6.5 Substrate (29 x 29 x 1.18 mm) Kx Ky Kz 18 18 1.0 W/m*K W/m*K
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 94 Freescale Semiconductor
Thermal
Table 67. MPC8533EThermal Model (continued)
Conductivity Value Solder and Air (29 x 29 x 0.58 mm) Kx Ky Kz 0.034 0.034 12.1 W/m*K Units
Bump Underfill
Die Substrate
Section A-A
Solder/Air
A
A
Top View
Figure 56. System Level Thermal Model for MPC8533E (Not to Scale)
The Flotherm library files of the parts have a dense grid to accurately capture the laminar boundary layer for flow over the part in standard JEDEC environments, as well as the heat spreading in the board under the package. In a real system, however, the part will require a heat sink to be mounted on it. In this case, the predominant heat flow path will be from the die to the heat sink. Grid density lower than currently in the package library file will suffice for these simulations. The user will need to determine the optimal grid for their specific case.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 95
Thermal
20.3
Thermal Management Information
This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design--the heat sink, airflow, and thermal interface material. The MPC8533E implements several features designed to assist with thermal management, including the temperature diode. The temperature diode allows an external device to monitor the die temperature in order to detect excessive temperature conditions and alert the system; see Section 20.3.4, "Temperature Diode," for more information. The recommended attachment method to the heat sink is illustrated in Figure 57. The heat sink should be attached to the printed-circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force (45 Newton).
FC-PBGA Package Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material
Die
Printed-Circuit Board
Figure 57. Package Exploded Cross-Sectional View with Several Heat Sink Options
The system board designer can choose between several types of heat sinks to place on the device. There are several commercially-available heat sinks from the following vendors: Aavid Thermalloy 603-224-9988 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Advanced Thermal Solutions 781-769-2800 89 Access Road #27. Norwood, MA02062 Internet: www.qats.com Alpha Novatech 408-567-8082 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 96 Freescale Semiconductor
Thermal
International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Millennium Electronics (MEI) Loroco Sites 671 East Brokaw Road San Jose, CA 95112 Internet: www.mei-thermal.com Tyco Electronics Chip CoolersTM P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com
818-842-7277
408-436-8770
800-522-6752
603-635-2800
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Several heat sinks offered by Aavid Thermalloy, Advanced Thermal Solutions, Alpha Novatech, IERC, Chip Coolers, Millennium Electronics, and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, that will allow the MPC8533E to function in various environments.
20.3.1
Internal Package Conduction Resistance
For the packaging technology, shown in Table 65, the intrinsic internal conduction thermal resistance paths are as follows: * The die junction-to-case thermal resistance * The die junction-to-board thermal resistance
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Thermal
Figure 58 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
External Resistance Radiation Convection
Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads
Printed-Circuit Board
External Resistance
Radiation
Convection
(Note the internal versus external package resistance.)
Figure 58. Package with Heat Sink Mounted to a Printed-Circuit Board
The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms.
20.3.2
Thermal Interface Materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 59 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a thermal resistance approximately six times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 57). Therefore, the synthetic grease offers the best thermal performance, especially at the low interface pressure.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 98 Freescale Semiconductor
Thermal
2
Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease
Specific Thermal Resistance (K-in.2/W)
1.5
1
0.5
0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi)
Figure 59. Thermal Performance of Select Thermal Interface Materials
The system board designer can choose between several types of thermal interface. There are several commercially-available thermal interfaces provided by the following vendors: Chomerics, Inc. 781-935-4850 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation 800-248-2481 Corporate Center P.O.Box 999 Midland, MI 48686-0997 Internet: www.dow.com Shin-Etsu MicroSi, Inc. 888-642-7674 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company 800-347-4572 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 99
Thermal
Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com
888-246-9050
20.3.3
Heat Sink Selection Examples
The following section provides a heat sink selection example using one of the commercially available heat sinks. For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: TJ = TI + TR + (JC + INT + SA) x PD where TJ is the die-junction temperature TI is the inlet cabinet ambient temperature TR is the air temperature rise within the computer cabinet JC is the junction-to-case thermal resistance INT is the adhesive or interface material thermal resistance SA is the heat sink base-to-ambient thermal resistance PD is the power dissipated by the device During operation the die-junction temperatures (TJ) should be maintained within the range specified in Table 2. The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (TI) may range from 30 to 40C. The air temperature rise within a cabinet (TR) may be in the range of 5 to 10C. The thermal resistance of the thermal interface material (INT) may be about 1C/W. Assuming a TI of 30C, a TR of 5C, a FC-PBGA package JC = 0.1, and a power consumption (PD) of 5, the following expression for TJ is obtained: Die-junction temperature: TJ = 30C + 5C + (0.1C/W + 1.0C/W + SA) x PD The heat sink-to-ambient thermal resistance (SA) versus airflow velocity for a Thermalloy heat sink #2328B is shown in Figure 60. Assuming an air velocity of 1 m/s, we have an effective SA+ of about 5C/W, thus TJ = 30 + 5C + (0.1C/W + 1.0C/W + 5C/W) x 5 resulting in a die-junction temperature of approximately 66, which is well within the maximum operating temperature of the component.
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Thermal
8
7 Heat Sink Thermal Resistance (C/W)
Thermalloy #2328B Pin-fin Heat Sink (25 x 28 x 15 mm)
6
5
4
3
2
1 0 0.5 1 1.5 2 2.5 3 3.5
Figure 60. Approach Air Velocity (m/s)
20.3.4
Temperature Diode
The MPC8533E has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as Analog Devices, ADT7461TM). These devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment. It is recommended that each device be individually calibrated. The following are voltage forward biased range of the on-board temperature diode: Vf > 0.40 V Vf < 0.90 V An approximate value of the ideality may be obtained by calibrating the device near the expected operating temperature. The ideality factor is defined as the deviation from the ideal diode equation: qVf nKT - 1 Ifw = Is e Another useful equation is: KT I VH - VL = n q ln IH L where: Ifw = Forward current
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System Design Information
Is = Saturation current Vd = Voltage at diode Vf = Voltage forward biased VH = Diode voltage while IH is flowing VL = Diode voltage while IL is flowing IH = Larger diode bias current IL = Smaller diode bias current q = Charge of electron (1.6 x 10 -19 C) n = Ideality factor (normally 1.0) K = Boltzman's constant (1.38 x 10-23 Joules/K) T = Temperature (Kelvins) The ratio of IH to IL is usually selected to be 10:1. The above simplifies to the following: VH - VL = 1.986 x 10-4 x nT Solving for T, the equation becomes: nT = VH - VL 1.986 x 10-4
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the MPC8533E.
21.1
System Clocking
This device includes six PLLs: * The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in Section 19.2, "CCB/SYSCLK PLL Ratio." * The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e500 core clock and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 19.3, "e500 Core PLL Ratio." * The PCI PLL generates the clocking for the PCI bus. * The local bus PLL generates the clock for the local bus. * There are two PLLs for the SerDes block.
21.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CORE, AVDD_PCI, AVDD_LBIU, and AVDD_SRDS, respectively). The AVDD
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System Design Information
level should always be equivalent to VDD, and preferably these voltages will be derived directly from VDD through a low frequency filter scheme such as the following. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent filter circuits per PLL power supply as illustrated in Figure 61, one to each of the AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV DD pin, which is on the periphery of 783 FC-PBGA the footprint, without the inductance of vias. Figure 61 shows the PLL power supply filter circuit.
V DD 10 2.2 F 2.2 F Low ESL Surface Mount Capacitors GND AVDD
Figure 61. MPC8533E PLL Power Supply Filter Circuit
The AVDD_SRDSn signals provide power for the analog portions of the SerDes PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in Figure 62. For maximum effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be near the AVDD_SRDSn balls. The 0.003-F capacitor is closest to the balls, followed by the 1-F capacitor, and finally the 1- resistor to the board supply plane. The capacitors are connected from AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide, and direct.
1.0 SVDD 2.2 F1 2.2 F1 0.003 F AV DD_SRDS
GND Note: 1. An 0805 sized capacitor is recommended for system initial bring-up.
Figure 62. SerDes PLL Power Supply Filter Circuit
Note the following: * AVDD_SRDS should be a filtered version of SVDD. * Signals on the SerDes interface are fed from the XVDD power plane.
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System Design Information
21.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8533E system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD, and LVDD pin of the device. These decoupling capacitors should receive their power from separate VDD, TVDD, BVDD, OVDD, GVDD, and LVDD; and GND power planes in the PCB, utilizing short low impedance traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, TVDD, BVDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors--100-330 F (AVX TPS tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor for best values and types and quantity of bulk capacitors.
21.4
SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. * First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible. * Second, there should be a 1-F ceramic chip capacitor on each side of the device. This should be done for all SerDes supplies. * Third, between the device and any SerDes voltage regulator there should be a 10-F, low equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-F, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.
21.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active low inputs should be tied to VDD, TVDD, BVDD, OVDD, GVDD, and LVDD as required. All unused active high inputs should be connected to GND. All NC (no connect) signals must
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System Design Information
remain unconnected. Power and ground connections must be made to all external VDD, TVDD, BVDD, OVDD, GVDD, and LVDD, and GND pins of the device.
21.6
Pull-Up and Pull-Down Resistor Requirements
The MPC8533E requires weak pull-up resistors (2-10 k is recommended) on open drain type pins including I2C pins and MPIC interrupt pins. Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 65. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. The following pins must NOT be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1] and TEST_SEL pins must be set to a proper state during POR configuration. Refer to the pinout listing table (Table 57) for more details. Refer to the PCI 2.2 Local Bus Specifications, for all pullups required for PCI.
21.7
Output Buffer DC Impedance
The MPC8533E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 63). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
OV DD
RN
SW2 Data Pad SW1
RP
OGND
Figure 63. Driver Impedance Measurement
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 105
System Design Information
Table 68 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD, nominal OVDD, 90C.
Table 68. Impedance Characteristics
Local Bus, Ethernet, DUART, Control, Configuration, Power Management 43 Target 43 Target
Impedance
PCI
DDR DRAM
Symbol
Unit
RN RP
25 Target 25 Target
20 Target 20 Target
Z0 Z0
W W
Note: Nominal supply voltages. See Table 1.
21.8
Configuration Pin Muxing
The MPC8533E provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k. This value should permit the 4.7-k resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage level puts the device into the default state and external resistors are needed only when non-default settings are required by the user. Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices.
21.9
JTAG Configuration Signals
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 65. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors built on Power ArchitectureTM technology. The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 106 Freescale Semiconductor
System Design Information
using only the TCK and TMS signals, generally systems will assert TRST during the power-on reset flow. Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the common on-chip processor (COP) function. The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 65 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. The COP interface has a standard header, shown in Figure 64, for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed. There is no standardized way to number the COP header; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 64 is common to all known emulators.
21.9.1
Termination of Unused Signals
If the JTAG interface and COP header will not be used, Freescale recommends the following connections: * TRST should be tied to HRESET through a 0-k isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in Figure 65. If this is not possible, the isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations. * No pull-up/pull-down is required for TDI, TMS, or TDO.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 107
System Design Information
COP_TDO COP_TDI COP_RUN/STOP COP_TCK COP_TMS COP_SRESET COP_HRESET COP_CHKSTP_OUT
1 3 5 7 9 11 13 15
2 4 6 8 10 12 KEY No pin 16
NC COP_TRST COP_VDD_SENSE COP_CHKSTP_IN NC NC
GND
Figure 64. COP Connector Physical Pinout
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 108 Freescale Semiconductor
System Design Information
OV DD SRESET HRESET 10 k SRESET 6 HRESET1
From Target Board Sources (if any)
10 k
13 11
COP_HRESET COP_SRESET
B
5
10 k
A
10 k 10 k 10 k TRST1
1 3 5 7 9 11
2 4 6 8 10 12
KEY
4 6 5 COP Header 15 14 3
COP_TRST COP_VDD_SENSE2 NC COP_CHKSTP_OUT 10 k 10 k COP_CHKSTP_IN 10
CKSTP_OUT
13 No pin 15 16
8 COP_TMS 9 COP_TDO COP_TDI COP_TCK 7 2 10 12 16 NC NC
4
CKSTP_IN TMS TDO TDI 10 k TCK
COP Connector Physical Pinout
1 3
Notes: 1. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown here. 2. Populate this with a 10- resistor for short-circuit/current-limiting protection. 3. The KEY location (pin 14) is not physically present on the COP header. 4. Although pin 12 is defined as a No Connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity. 5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B. 6. Asserting SRESET causes a machine check interrupt to the e500 core.
Figure 65. JTAG Interface Connection
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 109
System Design Information
21.10 Guidelines for High-Speed Interface Termination
21.10.1 SerDes Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. However, the SerDes must always have power applied to its supply pins. The following pins must be left unconnected (float): * SD_TX[0:7] * SD_TX[0:7] The following pins must be connected to GND: * SD_RX[0:7] * SD_RX[0:7] * SD_REF_CLK * SD_REF_CLK
21.10.2 SerDes Interface Partly Unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as described in this section. The following pins must be left unconnected (float) if not used: * SD_TX[0:7] * SD_TX[0:7] The following pins must be connected to GND if not used: * SD_RX[0:7] * SD_RX[0:7] * SD_REF_CLK * SD_REF_CLK
21.11 Guideline for PCI Interface Termination
PCI termination if not used at all is done as follows. Option 1 * If PCI arbiter is enabled during POR, * All AD pins will be driven to the stable states after POR. Therefore, all ADs pins can be floating. * All PCI control pins can be grouped together and tied to OVDD through a single 10-k resistor. * It is optional to disable PCI block through DEVDISR register after POR reset. Option 2 * If PCI arbiter is disabled during POR,
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 110 Freescale Semiconductor
Device Nomenclature
* *
All AD pins will be in the input state. Therefore, all ADs pins need to be grouped together and tied to OVDD through a single (or multiple) 10-k resistor(s). All PCI control pins can be grouped together and tied to OVDD through a single 10-k resistor.
21.12 Guideline for LBIU Termination
If the LBIU parity pins are not used, the following list shows the termination recommendation: * For LDP[0:3]: tie them to ground or the power supply rail via a 4.7-k resistor. * For LPBSE: tie it to the power supply rail via a 4.7-k resistor (pull-up resistor).
22 Device Nomenclature
Ordering information for the parts fully covered by this hardware specifications document is provided in Section 22.3, "Part Marking." Contact your local Freescale sales office or regional marketing team for order information.
22.1
Industrial and Commercial Tier Qualification
The MPC8533E device has been tested to meet the commercial tier qualification. Table 69 provides a description for commercial and industrial qualifications.
Table 69. Commercial and Industrial Description
Tier1 Commercial Industrial Typical Application Use Time 5 years 10 years Power-On Hours Example of Typical Applications
Part-time/ Full-Time PC's, consumer electronics, office automation, SOHO networking, portable telecom products, PDA's, etc. Typically Full-Time Installed telecom equipment, work stations, servers, warehouse equipment, etc.
Note: 1. Refer to Table 2 for operating temperature ranges. Temperature is independent of tier and varies per product.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 111
Device Nomenclature
22.2
Nomenclature of Parts Fully Addressed by this Document
Table 70. Device Nomenclature
Table 70 provides the Freescale part numbering nomenclature for the MPC8533E.
MPC
nnnn
E
C
HX
Package1 VT = FC-PBGA (lead free)
AA
Processor Frequency2
X
Platform Frequency
B
Revision Level Contact local Freescale sales office
Product Part Encryption Temperature Range Code Identifier Acceleration MPC 8533 Blank = not included E = included Blank = 0 to 90C
F = 333 MHz AL = 667 MHz AN = 800 MHz G = 400 MHz AQ = 1000 MHz J = 533 MHz AR = 1067 MHz
Notes: 1. See Section 18, "Package Description," for more information on available package types. 2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by part number specifications may support other maximum core frequencies.
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 112 Freescale Semiconductor
Device Nomenclature
22.3
Part Marking
Parts are marked as in the example shown in Figure 66.
MPCnnnnCHXAAXB
MMMMM CCCCC ATWLYYWW
FC-PBGA Notes: MMMMM is the 5-digit mask number. ATWLYYWW is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 66. Part Marking for FC-PBGA Device
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 113
Document Revision History
23 Document Revision History
Table 71 provides a revision history for the MPC8533E hardware specification.
Table 71. MPC8533E Document Revision History
Revision 3 2 Date 11/2009 01/2009 Substantive Change(s) * Update Section 20.3.4, "Temperature Diode," * Update Table 56 Package Parameters from 95.5%sn to 96.5%sn * * Update power number table to include 1067 MHz/533 MHz power numbers. * Remove Part number tables from Hardware spec. The part numbers are available on Freescale web site product page. * Removed I/O power numbers from the Hardware spec. and added the table to bring-up guide applacation note * Updated RX_CLK duty cycle min, and max value to meet the industry standard GMII duty cycle. * In Table 35, removed note 1 and renumbered remaining note. * Update paragraph Section 21.3, "Decoupling Recommendations * Update tDDKHMP, tDDKHME in Table 18 * Update Figure 5 DDR Output Timing Diagram Correction in Table 18 DDR SDRAM Output AC Timing Specifications tMCK Max value Improvement to Section 16, "High-Speed Serial Interfaces (HSSI) Update Figure 55 Mechanical Dimensions Correction in Table 43 Local Bus General Timing Parameters--PLL Bypassed Initial release.
1
06/2008
0
04/2008
MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 114 Freescale Semiconductor
Document Revision History
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MPC8533E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 115
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Document Number: MPC8533EEC Rev. 3 11/2009

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